Patent US4495593A successfully refreshed from Google Patents.
US4495593A
Expired / Lapsed
US
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Multiple bit encoding technique for combinational multipliers
Assignee: HP Inc
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Filing: 1982-07-01
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Granted: 1985-01-22
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Expires: 2002-07-01
Abstract
Abstract A four member encoding set is disclosed which allows the construction of combinational monolithic multipliers with a significant reduction in the number of devices required. The reduced device and wire count in the present technique allows a multiplier circuit of any given size to be made less expensively or alternatively allows a larger precision multiplier to be constructed.
Inventors
- 👤 Frederick A. Ware
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:10
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/533; G06F7/5334; G06F7/5336; G06F7/5338
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
291 words
An apparatus for multiplying first and second binary operands each having a nominal length of N bits where one of said bits of each operand may designate the sign of said operand comprising: means for grouping pairs of bits of said first binary operand; means for supplying a first carry in signal which is a 0; means for encoding the first pair of bits of said first binary operand and said first carry-in signal into one member of a set of only four multiplier digits and a first carry-out signal; means for passing the carry-out signal of one pair of bits of said first binary operand to the next subsequent pair of bits as the carry-in signal of said next subsequent pair of bits; means for encoding said subsequent pairs of bits and said subsequent carry-in signals into a member of said set of only four multiplier digits and a further carry-out signal; means for generating the partial products of said second binary operand and one of said four multiplier digits of said encoding set for each pair of bits of said first binary operand; means for extending said sign bit of said partial products; means for shifting said sign extended partial products by an amount equal to the weight of the less significant bit of the corresponding pair of bits of said first binary operand; means for summing said shifted sign extended partial products; and means for shifting said second binary operand by an amount equal to the weight of the more significant bit of the most significant pair of bits of said first binary operand, and adding said shifted second binary operand to said sum of shifted sign extended partial products when the final carry-out signal is a 1.
Claim 2
Independent Claim
291 words
An apparatus for multiplying first and second binary operands each having a nominal length of N bits where one of said bits of each operand may designate the sign of said operand comprising: means for grouping pairs of bits of said first binary operand; means for supplying a first carry in signal which is a 0; means for encoding the first pair of bits of said first binary operand and said first carry-in signal into one member of a set of only four multiplier digits and a first carry-out signal; means for passing the carry-out signal of one pair of bits of said first binary operand to the next subsequent pair of bits as the carry-in signal of said next subsequent pair of bits; means for encoding said subsequent pairs of bits and said subsequent carry-in signals into a member of said set of only four multiplier digits and a further carry-out signal; means for generating the partial products of said second binary operand and one of said four multiplier digits of said encoding set for each pair of bits of said first binary operand; means for extending said sign bit of said partial products; means for shifting said sign extended partial products by an amount equal to the weight of the less significant bit of the corresponding pair of bits of said first binary operand; means for summing said shifted sign extended partial products; and means for shifting said second binary operand by an amount equal to the weight of the more significant bit of the most significant pair of bits of said first binary operand, and adding said shifted second binary operand to said sum of shifted sign extended partial products when the final carry-out signal is a 1.
Claim 3
Dependent Claim
62 words
An apparatus as in claim 1 when said first operand is negative further comprising: means for shifting said second binary operand by an amount equal to the weight of the more significant bit of said pairs of bits of said first binary operand; and means for substracting said shifted second binary operand from said sum of said shifted sign extended partial products.
Claim 4
Dependent Claim
20 words
An apparatus as in claim 1 wherein said four multiplier digits comprise the set of +2, +1, 0, and -1.
Claim 5
Independent Claim
274 words
A method for multiplying first and second binary operands each having a nominal length of N bits where one of said bits of each operand may designate the sign of said operand comprising the steps of: grouping pairs of bits of said first binary operand; supplying a first carry-in signal which is a 0; encoding the first pair of bits of said first binary operand and said first carry-in signal into one member of a set of only four multiplier digits and a first carry-out signal; passing the carry-out signal of one pair of bits of said first binary operand to the next subsequent pair of bits as the carry-in signal of said next subsequent pair of bits; encoding said subsequent pairs of bits and said subsequent carry-in signals into a member of said set of only four multiplier digits and a further carry-out signal; generating the partial products of said second binary operand and one of said four multiplier digits of said encoding set for each pair of bits of said first binary operand; extending said sign bit of said partial products; shifting said sign extended partial products by an amount equal to the weight of the less significant bit of the corresponding pair of bits of said first binary operand; summing said shifted sign extended partial products; and shifting said second binary operand by an amount equal to the weight of the more significant bit of the most significant pair of bits of said first binary operand, and adding said shifted second binary operand to said sum of shifted sign extended partial products when the final carry out signal is a 1.
Claim 6
Independent Claim
274 words
A method for multiplying first and second binary operands each having a nominal length of N bits where one of said bits of each operand may designate the sign of said operand comprising the steps of: grouping pairs of bits of said first binary operand; supplying a first carry-in signal which is a 0; encoding the first pair of bits of said first binary operand and said first carry-in signal into one member of a set of only four multiplier digits and a first carry-out signal; passing the carry-out signal of one pair of bits of said first binary operand to the next subsequent pair of bits as the carry-in signal of said next subsequent pair of bits; encoding said subsequent pairs of bits and said subsequent carry-in signals into a member of said set of only four multiplier digits and a further carry-out signal; generating the partial products of said second binary operand and one of said four multiplier digits of said encoding set for each pair of bits of said first binary operand; extending said sign bit of said partial products; shifting said sign extended partial products by an amount equal to the weight of the less significant bit of the corresponding pair of bits of said first binary operand; summing said shifted sign extended partial products; and shifting said second binary operand by an amount equal to the weight of the more significant bit of the most significant pair of bits of said first binary operand, and adding said shifted second binary operand to said sum of shifted sign extended partial products when the final carry out signal is a 1.
Claim 7
Dependent Claim
61 words
A method as in claim 4 when said first operand is negative further comprising the steps of: shifting said second binary operand by an amount equal to the weight of the more significant bit of said pairs of bits of said first binary operand; and subtracting said shifted second binary operand from said sum of said shifted sign extended partial products.
References Cited (Backward Citations)
US4122527A
Cited
US4110832A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-22 | 1988-07-23 | 1989-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-22 | 1992-07-23 | 1993-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-22 | 1996-07-23 | 1997-01-22 | $7700.00 | Window Closed / Lapsed |