Patent US4495426A successfully refreshed from Google Patents.
US4495426A
Expired / Lapsed
US
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Low power inverter circuit
Assignee: Texas Instruments Inc
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Filing: 1981-12-24
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Granted: 1985-01-22
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Expires: 2001-12-24
Abstract
Abstract A circuit that precharges a node and conditionally discharges the node according to the value of an input. This circuit also includes a device to isolate the node from the output line during precharge. This circuit can be fabricated as a positive channel metal oxide field effect transistor and can be structured to perform the logic function of an inverter or an NAND or NOR gate in simple form. This circuit also includes a capacitor that is connected to the precharge node such that additional charge provided by the clocking circuit is used to add charge to the node such that the charge at the node is greater than the charge provided by the circuit power supply alone.
Inventors
- 👤 Jerald G. Leach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:04
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
247 words
A low power logic circuit comprising: a node; a voltage supply for supplying voltage to the low power logic circuit; an input line means for receiving an input signal with a first and second logic level; an output line; a first and second clock means for providing a first and second clock signal, the first clock signal having an antiphase relationship with the second clock signal; first circuit means, connected to said first and second clock means and said voltage supply for precharging the node with the supply voltage in response to the first clock signal, and conditionally discharging the node in response to the second clock signal; a second circuit means connected to said input line means for discharging said node upon an occurrence of the first logic level and the first circuit means conditioned to discharge said node; and third circuit means connected to said second circuit means, said node, said input line means, said second clock means, said power supply and said output line, for isolating said output line from the node, in response to the second clock signal by disabling the third circuit means when the first clock signal enables the first circuit means, the third circuit means includes: switching means, connected to said power supply and said node for providing an output signal to said output line upon an occurrence of a preselected change of level of said node with an occurrence of a preselected clock level of said second clock signal.
Claim 2
Dependent Claim
247 words
A low power logic circuit comprising: a node; a voltage supply for supplying voltage to the low power logic circuit; an input line means for receiving an input signal with a first and second logic level; an output line; a first and second clock means for providing a first and second clock signal, the first clock signal having an antiphase relationship with the second clock signal; first circuit means, connected to said first and second clock means and said voltage supply for precharging the node with the supply voltage in response to the first clock signal, and conditionally discharging the node in response to the second clock signal; a second circuit means connected to said input line means for discharging said node upon an occurrence of the first logic level and the first circuit means conditioned to discharge said node; and third circuit means connected to said second circuit means, said node, said input line means, said second clock means, said power supply and said output line, for isolating said output line from the node, in response to the second clock signal by disabling the third circuit means when the first clock signal enables the first circuit means, the third circuit means includes: switching means, connected to said power supply and said node for providing an output signal to said output line upon an occurrence of a preselected change of level of said node with an occurrence of a preselected clock level of said second clock signal.
Claim 3
Dependent Claim
34 words
The low power logic circuit according to claim 1, wherein said first circuit means includes a capacitor connected between the second clock means and the node to provide an additional charge to said node.
Claim 4
Dependent Claim
21 words
The low power logic circuit according to claim 1, wherein said first, second and third circuit means comprises: field effect transistors.
Claim 5
Dependent Claim
26 words
The low power logic circuit according to claim 3, wherein said first, second and third circuit means comprises: positive channel metal oxide semiconductor field effect transistors.
Claim 6
Dependent Claim
27 words
The low power logic circuit according to claim 4 wherein the first, second and third circuit means comprises: a monolithically integrated circuit on a single semiconductor substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-22 | 1988-07-23 | 1989-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-22 | 1992-07-23 | 1993-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-22 | 1996-07-23 | 1997-01-22 | $7700.00 | Window Closed / Lapsed |