Abstract Division by fractions is accomplished with a counter (Z) presettable to integers and a digitally adjustable delay line (V) following this counter. The fractional parts (b) of the divisor, which are held in decimal point representation (a+0.b) in a divisor register (R), are applied to a first adder (A1) followed by a buffer memory (S), and the integral parts (a) of this divisor are applied to a second adder (A2). The output of the buffer memory (S) is coupled to the set input (Es) of the delay line (V) and to the second input (E2) of the first adder (A1). Thus, at the input of the delay line (V), the number corresponding to the fractional parts (b) is continuously increased by the fractional parts (b) until the overflow output (Ao) of the first adder (A1) provides a signal which is applied to the least significant digit (LB) of the first input (E1) of the second adder (A2). One unit is thus added to the integral parts (a), and the counter (Z) counts one additional digit for one cycle. For arbitrary fractional divisors, the maximum phase-jitter amplitude is equal to the smallest adjustable time delay and, hence, considerably smaller than the clock period (T') of the signal to be divided (F).
Frequency divider presettable to fractional divisors (c/e) and including a counter (Z) presettable to integers, characterized by the following features: Those stages (Rb) of a divisor register (R) holding the fractional parts (b) of the divisor (c/e) in decimal point representation (a+0.b) are connected to the first input (E1) of a first adder (A1) having its output (A) coupled to the input of a buffer memory (S); the output of the buffer memory (S) is coupled to the second input (E2) of the first adder (A1) and to the set input (Es) of a digitally adjustable delay line (V) whose setting-step width is equal to the period (T) of the divider input signal (F) divided by the nominator (e) of the divisor (c/e), and whose input is connected to the maximum-count output (Am) of the counter (Z), and the overflow (Ao) of the first adder (A1) is coupled to the least significant digit (LB) of the first input (E1) of a second adder (A2), whose second input (E2) is connected to those stages (Ra) of the divisor register (R) holding the integral parts (a) of the divisor (c/e), and whose output (A2) is coupled to the set input (Es) of the counter (Z), and the enable input (En) of the buffer memory (S) is connected to one of the count outputs (An) of the counter (Z), which lie before the maximum-count output (An).
Claim 2
Dependent Claim
233 words
Frequency divider presettable to fractional divisors (c/e) and including a counter (Z) presettable to integers, characterized by the following features: Those stages (Rb) of a divisor register (R) holding the fractional parts (b) of the divisor (c/e) in decimal point representation (a+0.b) are connected to the first input (E1) of a first adder (A1) having its output (A) coupled to the input of a buffer memory (S); the output of the buffer memory (S) is coupled to the second input (E2) of the first adder (A1) and to the set input (Es) of a digitally adjustable delay line (V) whose setting-step width is equal to the period (T) of the divider input signal (F) divided by the nominator (e) of the divisor (c/e), and whose input is connected to the maximum-count output (Am) of the counter (Z), and the overflow (Ao) of the first adder (A1) is coupled to the least significant digit (LB) of the first input (E1) of a second adder (A2), whose second input (E2) is connected to those stages (Ra) of the divisor register (R) holding the integral parts (a) of the divisor (c/e), and whose output (A2) is coupled to the set input (Es) of the counter (Z), and the enable input (En) of the buffer memory (S) is connected to one of the count outputs (An) of the counter (Z), which lie before the maximum-count output (An).