Nonvolatile read only memory device

Claim 2

A nonvolatile read only memory comprising: a word line a nonvolatile memory cell transistor connected at the gate to said word line; first and second MOS transistors; first bias circuit for biasing through said first MOS transitor a common read-out node connected to the drain of said memory cell transistor; a reference cell transistor for detecting a threshold voltage of said memory cell transistor; a constant potential circuit for applying to the gate of said reference cell transistor a constant voltage which is higher than the threshold voltage of said reference cell transistor and independent of a power source voltage for reading out; a second bias circuit for biasing through said second MOS transistor the output of said reference cell transistor; and a differential amplifier for amplifying a difference between voltage signals from said first and second bias circuits.

Claim 3

A nonvolatile read only memory comprising: a word line; a nonvolatile memory cell transistor connected at the gate to said word line; first and second MOS transistors; a first bias circuit for biasing through said first MOS transistor a common read-out node connected to the drain of said memory cell transistor; a reference cell transistor for detecting a threshold voltage of said memory cell transistor; a constant potential circuit for applying to the gate of said reference cell transistor a constant voltage which is higher than the threshold voltage of said reference cell transistor and independent of a power source voltage for reading out; a second bias circuit for biasing through said second MOS transistor the output of said reference cell transisotr; a differential amplifier for amplifying a difference between voltage signals from said first and second bias circuits; wherein said constant potential circuit includes a third MOS transistor of an enhancement type which receives at one end the power source voltage; a fourth MOS transistor of a depletion type which is connected at one end to the other end of said third MOS transistor and at the gate to its other end and to a reference potential; a fifth MOS transistor of a depletion type which is supplied at one end with the power source voltage, and connected at the gate to its other end and to the gate of said third MOS transistor; and a sixth nonvolatile MOS transistor which is connected at one end to the other end of said fifth MOS transistor, at the other end to a reference potential, and at the gate to a node between said third and fourth MOS transistors.

Claim 4

A nonvolatile read only memory comprising: a word line; a nonvolatile memory cell transistor connected at the gate to said word line; first and second MOS transistors; a first bias circuit for biasing through said first MOS transistor a common read-out node connected to the drain of said memory cell transistor; a reference cell transistor for detecting a threshold voltage of said memory cell transistor; a constant potential circuit for applying to the gate of said reference cell transistor a constant voltage which is higher than the threshold voltage of said reference cell transistor and independent of a power source voltage for reading out; a second bias circuit for biasing through said second MOS transistor the output of said reference cell transisotr; a differential amplifier for amplifying a difference between voltage signals from said first and second bias circuits; wherein said constant potential circuit includes a third MOS transistor of an enhancement type which receives at one end the power source voltage; a fourth MOS transistor of a depletion type which is connected at one end to the other end of said third MOS transistor and at the gate to its other end and to a reference potential; a fifth MOS transistor of a depletion type which is supplied at one end with the power source voltage, and connected at the gate to its other end and to the gate of said third MOS transistor; and a sixth nonvolatile MOS transistor which is connected at one end to the other end of said fifth MOS transistor, at the other end to a reference potential, and at the gate to a node between said third and fourth MOS transistors.

Claim 5

A nonvolatile read only memory comprising: a word line; a nonvolatile memory cell transistor connected at the gate to said word line; first and second MOS transistors; a first bias circuit for biasing through said first MOS transistor a common read-out node connected to the drain of said memory cell transistor; a reference cell transistor for detecting a threshold voltage of said memory cell transistor; a constant potential circuit for applying to the gate of said reference cell transistor a constant voltage which is higher than the threshold voltage of said reference cell ransistor and independent of a power source voltage for reading out; a second bias circuit for biasing through said second MOS transistor the output of said reference cell transistor; a differential amplifier for amplifying a difference between voltage signals from said first and second bias circuits; wherein said constant potential circuit includes a third MOS transistor of a depletion type which is supplied at one end with the power source voltage; a fourth MOS transistor of an enhancement type which is connected at one end to the other end of said third MOS transistor, to its gate and to the gate of said third MOS transistor; and a fifth nonvolatile MOS transistor which is connected at one end to the other end of said fourth MOS transistor and to its gate, and at the other end to a reference potential.

Claim 6

A nonvolatile read only memory comprising: a word line; a nonvolatile memory cell transistor connected at the gate to said word line; first and second MOS transistors; a first bias circuit for biasing through said first MOS transistor a common read-out node connected to the drain of said memory cell transistor; a reference cell transistor for detecting a threshold voltage of said memory cell transistor; a constant potential circuit for applying to the gate of said reference cell transistor a constant voltage which is higher than the threshold voltage of said reference cell ransistor and independent of a power source voltage for reading out; a second bias circuit for biasing through said second MOS transistor the output of said reference cell transistor; a differential amplifier for amplifying a difference between voltage signals from said first and second bias circuits; wherein said constant potential circuit includes a third MOS transistor of a depletion type which is supplied at one end with the power source voltage; a fourth MOS transistor of an enhancement type which is connected at one end to the other end of said third MOS transistor, to its gate and to the gate of said third MOS transistor; and a fifth nonvolatile MOS transistor which is connected at one end to the other end of said fourth MOS transistor and to its gate, and at the other end to a reference potential.

Claim 7

A nonvolatile read only memory comprising: a word line; a nonvolatile memory cell transistor connected at the gate to said word line; a first bias circuit for biasing through a first MOS transistor a common read-out node connected to the drain of said memory cell transistor; a first reference cell transistor for reading out data of said memory cell transistor; a circuit for resistor division of a power source voltage for reading out, and supplying the divided voltage to the gate of said first reference cell transistor; a second reference cell transistor for detecting the threshold voltage of said memory cell transistor; a constant potential circuit for supplying to the gate of said second reference cell transistor a constant voltage which is higher than the threshold voltage of said second reference cell transistor and independent of said power source voltage for reading out; a second MOS transistor connected at one end to the output terminal of said first reference cell transistor; a third MOS transistor connected at one end to the output terminal of said second reference cell transistor; a second bias circuit connected to the other end of said second and third MOS transistor; a circuit for supplying control signals, which are related each other in an inverted manner, to the gate of said second and third MOS transistors; and a differential amplifier for amplifying a difference between the voltage signals from said first and second bias circuits.

Claim 8

A nonvolatile read only memory comprising: a word line; a nonvolatile memory cell transistor connected at the gate to said word line; a first bias circuit for biasing through a first MOS transistor a common read-out node connected to the drain of said memory cell transistor; a first reference cell transistor for reading out data of said memory cell transistor; a circuit for resistor division of a power source voltage for reading out, and supplying the divided voltage to the gate of said first reference cell transistor; a second reference cell transistor for detecting the threshold voltage of said memory cell transistor; a constant potential circuit for supplying to the gate of said second reference cell transistor a constant voltage which is higher than the threshold voltage of said second reference cell transistor and independent of said power source voltage for reading out; a second MOS transistor connected at one end to the output terminal of said first reference cell transistor; a third MOS transistor connected at one end to the output terminal of said second reference cell transistor; a second bias circuit connected to the other end of said second and third MOS transistor; a circuit for supplying control signals, which are related each other in an inverted manner, to the gate of said second and third MOS transistors; and a differential amplifier for amplifying a difference between the voltage signals from said first and second bias circuits.

Claim 9

A nonvolatile read only memory according to claim 4, wherein said constant potential circuit comprises: a fourth MOS transistor of an enhancement type which receives at one end the power source voltage; a fifth MOS transistor of a depletion type which is connected at one end to the other end of said fourth MOS transistor and at the gate and other end to a reference potential; a sixth MOS transistor of a depletion type which is supplied at one end with the power source voltage, and connected at the gate and at the other end to the gate of said fourth MOS transistor and an output terminal; and a seventh nonvolatile MOS transistor which is connected at one end to the other end of said sixth MOS transistor, at the other end to a reference potential, and at the gate to a node between said fourth and fifth MOS transistors.

Claim 10

A nonvolatile read only memory according to claim 4, wherein said constant potential circuit comprises: a fourth MOS transistor of a depletion type which is supplied at one end with the power source voltage; a fifth MOS transistor of an enhancement type which is connected at one end to the other end of said fourth MOS transistor, and to the gate per se and the gate of said fourth MOS transistor, a node between said fourth and fifth MOS transistors being connected to the output terminal; and a sixth nonvolatile MOS transistor which is connected at one end to the other end of said fifth MOS transistor and to the gate per se, and at the other end to a reference potential.

Claim 11

A nonvolatile read only memory according to claim 4, wherein said circuit for supplying control signals is connected to a terminal for supplying a control signal to supply a voltage higher than that in a normal operation.

Claim 12

A nonvolatile read only memory according to claim 7, wherein said circuit for supplying control signals comprises a plurality of inverters connected in series.

Claim 13

A nonvolatile read only memory according to claim 8, wherein said inverter connected to said terminal for supplying a control signal has a threshold voltage higher than a voltage used in a normal operation mode and comprises: a fourth MOS transistor which is supplied at one end with the power source voltage; and a fifth MOS transistor connected at one end to the gate and the other end of said fourth MOS transistor, supplied at the other end with a reference potential, and connected at the gate to said terminal for supplying a control signal.