Multi-device apparatus synchronized to the slowest device

Claim 2

A synchronous apparatus comprising: a plurality of devices for operating synchronously, each device having an output terminal for selectively generating thereon a first signal to indicate readiness to operate and a second signal to indicate completion of operation, each device further having an input terminal for receiving thereon a third signal for causing the device to operate and a fourth signal for causing the device to stop operating; and synchronizing means, having a plurality of input terminal means connected to the output terminals of the plurality of devices and output terminal means connected to the input terminals of the plurality of devices, adapted to initiate generating on its output terminal means the third signal upon sensing the first signal on all of its input terminal means and to continue to generate the third signal while the first signal is present on at least one of its input terminal means, the means further adapted to initiate generating on its output terminal means the fourth signal upon sensing the second signal on all of its input terminal means and for continuing to generate the fourth signal while the second signal is present on at least one of its input terminal means, thereby to synchronize the operation of the plurality of devices with the slowest of the plurality of devices.

Claim 3

The apparatus of claim 1 wherein the plurality of devices comprises at least one first-in first-out buffer memory.

Claim 4

The apparatus of claim 1 wherein the plurality of devices comprises at least one first-in first-out buffer memory, wherein the output terminal is an output register empty signal output terminal, and wherein the input terminal is a transfer off stack signal input terminal.

Claim 5

The apparatus of claim 1 wherein the plurality of devices comprises at least one first-in first-out buffer memory, wherein the output terminal is an input register full signal output terminal and wherein the input terminal is a transfer to stack signal input terminal.

Claim 6

The apparatus of claim 1 wherein the synchronizing means comprise a circuit for selectively producing the third and fourth signals as one of an AND and an OR combination of the first and second signals in response to the presence of one and the other, respectively, of the third and fourth signals at the output terminal means.

Claim 7

The apparatus of claim 1 wherein the synchronizing means comprise a circuit for initiating generation of the third signal as an AND combination of the first signals and for continuing generation of the third signal as an OR combination of the first signals, the circuit further for initiating generation of the fourth signal as an AND combination of the second signals and for continuing generation of the fourth signal as an OR combination of the second signals.

Claim 8

The apparatus of claim 1 wherein the synchronizing means comprise at least one full adder circuit.

Claim 9

The apparatus of claim 1 wherein the synchronizing means comprise at least one full adder circuit having a first and a second set of binary word input terminals, a carry input terminal, and a carry output terminal, such that the input terminal means of the synchronizing means include the first set of binary word input terminals and the carry input terminal, the output terminal means of the synchronizing means include the carry output terminal, and the second set of binary word input terminals are connected to the carry output terminal.

Claim 10

A synchronous apparatus for synchronizing transfers of data comprising: (A) a plurality of first-in first-out data buffer memories each having (1) an output terminal selectively having (i) a first signal level indicative of readiness to transfer data and (ii) a second signal level indicative of completion of data transfer, and (2) an input terminal for selectively assuming a first signal level to enable data transfer and a second signal level to disable data transfer; and (B) a logic circuit, connected from the input terminals to the output terminals of the plurality of first-in first-out buffer memories, for selectively generating on the input terminals (1) the first and second signal levels corresponding to an AND combination of the signal levels on the output terminals, and (2) the first and second signal levels corresponding to an OR combination of the signal levels on the output terminals, in response to the current signal level of the input terminals, whereby data transfers of the plurality of buffer memories are synchronized with data transfers of the slowest of the plurality of buffer memories.

Claim 11

A synchronous apparatus for synchronizing transfers of data comprising: (A) a plurality of first-in first-out data buffer memories each having (1) an output terminal selectively having (i) a first signal level indicative of readiness to transfer data and (ii) a second signal level indicative of completion of data transfer, and (2) an input terminal for selectively assuming a first signal level to enable data transfer and a second signal level to disable data transfer; and (B) a logic circuit, connected from the input terminals to the output terminals of the plurality of first-in first-out buffer memories, for selectively generating on the input terminals (1) the first and second signal levels corresponding to an AND combination of the signal levels on the output terminals, and (2) the first and second signal levels corresponding to an OR combination of the signal levels on the output terminals, in response to the current signal level of the input terminals, whereby data transfers of the plurality of buffer memories are synchronized with data transfers of the slowest of the plurality of buffer memories.

Claim 12

A synchronous apparatus for synchronizing transfers of data comprising: (A) a plurality of first-in first-out data buffer memories each having (1) an output terminal selectively having (i) a first signal level indicative of readiness to transfer data and (ii) a second signal level indicative of completion of data transfer, and (2) an input terminal for selectively assuming (i) a first signal level to enable data transfer and (ii) a second signal level to disable data transfer; and (B) at least one full adder circuit having (1) a first binary word input port and a carry input terminal connected to the output terminals of the plurality of buffer memories, (2) a carry output terminal connected to the input terminals of the plurality of buffer memories, and (3) a second binary word input port connected to the carry output terminal, whereby data transfers of the plurality of buffer memories are synchronized with data transfers of the slowest of the plurality of buffer memories.

Claim 13

A synchronous apparatus for synchronizing transfers of data comprising: (A) a plurality of first-in first-out data buffer memories each having (1) an output terminal selectively having (i) a first signal level indicative of readiness to transfer data and (ii) a second signal level indicative of completion of data transfer, and (2) an input terminal for selectively assuming (i) a first signal level to enable data transfer and (ii) a second signal level to disable data transfer; and (B) at least one full adder circuit having (1) a first binary word input port and a carry input terminal connected to the output terminals of the plurality of buffer memories, (2) a carry output terminal connected to the input terminals of the plurality of buffer memories, and (3) a second binary word input port connected to the carry output terminal, whereby data transfers of the plurality of buffer memories are synchronized with data transfers of the slowest of the plurality of buffer memories.

Claim 14

A synchronous apparatus for synchronizing transfers of data comprising: (A) a plurality of first-in first-out data buffer memories each having (1) an output terminal selectively having (i) a first signal level indicative of readiness to transfer data and (ii) a second signal level indicative of completion of data transfer, and (2) an input terminal for selectively assuming (i) a first signal level to enable data transfer and (ii) a second signal level to disable data transfer; and (B) a plurality of full adder circuits each having a first and a second plurality of binary input terminals, a carry input terminal, and a carry output terminal, the full adder circuits being configured such that (1) (i) all but one of the carry input terminals and the first plurality of binary input terminals of all but a first one of the full adder circuits, and (ii) the carry input terminal and the first plurality of binary input terminals of the first one of the full adder circuits, are connected to the output terminals of the buffer memories, (2) the carry output terminals of all but a last one of the full adder circuits are connected to the ones of the carry input terminals and the first plurality of binary input terminals not connected to the output terminals of the buffer memories, (3) the carry output terminal of the last one of the full adder circuits is connected to the output terminals of the buffer memories and (4) the second plurality of binary input terminals of each full adder circuit is connected to the carry output terminal of the last one of the full adder circuits, whereby data transfers of the plurality of buffer memories are synchronized with data transfers of the slowest of the plurality of buffer memories.

Claim 15

A synchronous apparatus for synchronizing transfers of data comprising: (A) a plurality of first-in first-out data buffer memories each having (1) an output terminal selectively having (i) a first signal level indicative of readiness to transfer data and (ii) a second signal level indicative of completion of data transfer, and (2) an input terminal for selectively assuming (i) a first signal level to enable data transfer and (ii) a second signal level to disable data transfer; and (B) a plurality of full adder circuits each having a first and a second plurality of binary input terminals, a carry input terminal, and a carry output terminal, the full adder circuits being configured such that (1) (i) all but one of the carry input terminals and the first plurality of binary input terminals of all but a first one of the full adder circuits, and (ii) the carry input terminal and the first plurality of binary input terminals of the first one of the full adder circuits, are connected to the output terminals of the buffer memories, (2) the carry output terminals of all but a last one of the full adder circuits are connected to the ones of the carry input terminals and the first plurality of binary input terminals not connected to the output terminals of the buffer memories, (3) the carry output terminal of the last one of the full adder circuits is connected to the output terminals of the buffer memories and (4) the second plurality of binary input terminals of each full adder circuit is connected to the carry output terminal of the last one of the full adder circuits, whereby data transfers of the plurality of buffer memories are synchronized with data transfers of the slowest of the plurality of buffer memories.

Claim 16

A synchronous data transfer arrangement comprising a plurality of first-in first-out buffer memories each adapted to generate a readiness signal indicative of readiness to transfer data and a completion signal indicative of completion of data transfer and responsive to an enable signal to enable transfer operations and to a disable signal to disable transfer operations; and synchronizing means connected to said buffer memories and responsive to the concurrent appearance of said readiness signals to initiate and apply the enable signal to all of said memories simultaneously and to continue application of said enable signal while a readiness signal is generated by any one of said memories, the synchronizing means further responsive to the concurrent appearance of said completion signals to initiate and apply the disable signal to all of said memories simultaneously and to continue application of said disable signal while a completion signal is generated by any one of said memories.

Claim 17

A synchronous data transfer arrangement comprising a plurality of first-in first-out buffer memories each adapted to generate a readiness signal indicative of readiness to transfer data and a completion signal indicative of completion of data transfer and responsive to an enable signal to enable transfer operations and to a disable signal to disable transfer operations; and synchronizing means connected to said buffer memories and responsive to the concurrent appearance of said readiness signals to initiate and apply the enable signal to all of said memories simultaneously and to continue application of said enable signal while a readiness signal is generated by any one of said memories, the synchronizing means further responsive to the concurrent appearance of said completion signals to initiate and apply the disable signal to all of said memories simultaneously and to continue application of said disable signal while a completion signal is generated by any one of said memories.

Claim 18

A data transfer arrangement for transferring data between a pair of data buses, comprising a plurality of buffer memories each having an input register connected to one of the data buses for receiving data therefrom, a memory stack connected to the input register, and an output register connected to the memory stack and to the other of the data buses for transmitting data thereon, each buffer memory adapted to generate an input readiness signal and an output readiness signal and each responsive to an input transfer signal to transfer data from the input register to the memory stack and responsive to an output transfer signal to transfer data from the memory stack to the output register; synchronizing means responsive to the concurrent generation of said input readiness signals by all of said memories to initiate and apply said input transfer signal to all of said memories simultaneously and to continue the application of said input transfer signal as long as at least one of said memories is generating said input readiness signal, and responsive to the concurrent generation of said output readiness signals by all of said memories to initiate and apply said output transfer signal to all of said memories simultaneously and to continue the application of said output transfer signal as long as at least one of said memories is generating said output readiness signal; whereby data is transferred between two data buses by means of a plurality of independent buffer memories acting in unison.

Claim 19

A data transfer arrangement for transferring data between a pair of data buses, comprising a plurality of buffer memories each having an input register connected to one of the data buses for receiving data therefrom, a memory stack connected to the input register, and an output register connected to the memory stack and to the other of the data buses for transmitting data thereon, each buffer memory adapted to generate an input readiness signal and an output readiness signal and each responsive to an input transfer signal to transfer data from the input register to the memory stack and responsive to an output transfer signal to transfer data from the memory stack to the output register; synchronizing means responsive to the concurrent generation of said input readiness signals by all of said memories to initiate and apply said input transfer signal to all of said memories simultaneously and to continue the application of said input transfer signal as long as at least one of said memories is generating said input readiness signal, and responsive to the concurrent generation of said output readiness signals by all of said memories to initiate and apply said output transfer signal to all of said memories simultaneously and to continue the application of said output transfer signal as long as at least one of said memories is generating said output readiness signal; whereby data is transferred between two data buses by means of a plurality of independent buffer memories acting in unison.