US4493031A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory write protection using timers
Assignee: Nokia Bell Labs
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Filing: 1982-08-25
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Granted: 1985-01-08
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Expires: 2002-08-25
Abstract
Abstract A memory write-enable circuit is disclosed which protects data stored in a random access memory (RAM) from erroneous write commands. The circuit is enabled, permitting write commands to RAM for a fixed time interval, only when two predetermined control signals occur within a prescribed time period. The circuit is disabled either by the elapse of the fixed time interval or by a clear signal.
Inventors
- 👤 Vincent J. Silverio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:25
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1433
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
59 words
A memory write-enable circuit comprising: first means responsive to a first input signal for generating an enable signal, and a second means responsive to said enable signal and to a second input signal received within a first predetermined time interval of said first input signal for generating a write-enable signal for enabling the writing of data into a memory.
Claim 2
Dependent Claim
59 words
A memory write-enable circuit comprising: first means responsive to a first input signal for generating an enable signal, and a second means responsive to said enable signal and to a second input signal received within a first predetermined time interval of said first input signal for generating a write-enable signal for enabling the writing of data into a memory.
Claim 3
Dependent Claim
36 words
The memory write-enable circuit of claim 1 wherein said enable signal exists for said first predetermined time interval and said write-enable signal exists for a second predetermined time interval longer than said first predetermined time interval.
Claim 4
Dependent Claim
25 words
The memory write-enable circuit of claim 1 further comprising: decoder means for generating said first input signal and said second input signal from control signals.
Claim 5
Dependent Claim
30 words
The memory write-enable circuit of claim 3 wherein said decoder means generates said first input signal and said second input signal by decoding address signals on a memory address bus.
Claim 6
Dependent Claim
26 words
The memory write-enable circuit of claim 1 further including: a clear circuit responsive to a third signal for clearing said first means and said second means.
Claim 7
Dependent Claim
23 words
The memory write-enable circuit of claim 5 wherein said clear circuit generates said third signal by decoding signals on said memory address bus.
Claim 8
Dependent Claim
17 words
The memory write-enable circuit of claim 1 wherein said first and second means are monostable multivibrator circuits.
Claim 9
Independent Claim
56 words
A method of selectively enabling write commands to a memory circuit of a program controlled apparatus, the method comprising the steps of: detecting the occurrence of two control signals from said program controlled apparatus within a first time interval and enabling write commands to said memory circuit for a second time interval following said detecting step.
Claim 10
Independent Claim
56 words
A method of selectively enabling write commands to a memory circuit of a program controlled apparatus, the method comprising the steps of: detecting the occurrence of two control signals from said program controlled apparatus within a first time interval and enabling write commands to said memory circuit for a second time interval following said detecting step.
Claim 11
Dependent Claim
54 words
The method of claim 8 wherein said detecting step includes the steps of: starting a timer means external to said program controlled apparatus in response to a first control signal from said program controlled apparatus, and generating a second time interval in response to a second control signal occuring during said first timer interval.
Claim 12
Dependent Claim
28 words
The method of claim 8 further comprising the step of: terminating the first and second time intervals in response to a clear signal from said program controlled apparatus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-08 | 1988-07-09 | 1989-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-08 | 1992-07-09 | 1993-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-08 | 1996-07-09 | 1997-01-08 | $7700.00 | Window Closed / Lapsed |