US4332009A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory protection system
Assignee: STMicroelectronics lnc USA
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Filing: 1980-01-21
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Granted: 1982-05-25
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Expires: 2000-01-21
Abstract
Abstract A memory protect circuit (12) is provided for protecting inadvertent alteration of data stored in a data storage unit (32) of a data processing system (10). The data processing system (10) includes a microprocessor (14) for generating an address signal to selected storage locations of the storage unit (32) and for generating a key code prior to generation of the address signal. The write protect circuitry (12) includes decode circuitry (50) for receiving the key code and for generating a decoded key code. A latch (54) receives the decoded key code and generates a control signal upon receipt of the decoded key code. A NAND gate (62) receives the control signal and the address signal to generate an access signal for application to the storage unit (32) to permit alteration of data stored at a selected storage location of the storage unit (32) through a write operation. Latch (54) prevents generation of the control signal immediately following a write operation unit receipt by the decode circuitry (50) of a subsequently generated key code.
Inventors
- 👤 I. Steve Gerson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 13:01
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1433
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
170 words
A memory protect circuit for preventing inadvertent alteration of data stored in a storage unit of a data processing system having a processor for generating an address enable signal to enable an address signal to be applied to selected storage locations of the storage unit and for generating a key code prior to generation of the address enable signal comprising: receiving means for receiving the key code and for generating a decoded key code; latch means for receiving said decoded key code and for generating a control signal upon receipt of said decoded key code; means for receiving said control signal and the address enable signal to permit the address enable signal to be applied to the storage unit to permit alteration of data stored at the selected storage location of the storage unit through a write operation; and means for preventing generation of said control signal immediately following a write operation to thereby prevent subsequent write operations until receipt by said receiving means of a subsequently generated key code.
Claim 2
Dependent Claim
170 words
A memory protect circuit for preventing inadvertent alteration of data stored in a storage unit of a data processing system having a processor for generating an address enable signal to enable an address signal to be applied to selected storage locations of the storage unit and for generating a key code prior to generation of the address enable signal comprising: receiving means for receiving the key code and for generating a decoded key code; latch means for receiving said decoded key code and for generating a control signal upon receipt of said decoded key code; means for receiving said control signal and the address enable signal to permit the address enable signal to be applied to the storage unit to permit alteration of data stored at the selected storage location of the storage unit through a write operation; and means for preventing generation of said control signal immediately following a write operation to thereby prevent subsequent write operations until receipt by said receiving means of a subsequently generated key code.
Claim 3
Dependent Claim
18 words
The memory protect circuit of claim 1 wherein said means for receiving the key code comprises decode means.
Claim 4
Dependent Claim
19 words
The memory protect circuit of claim 1 wherein said means for receiving said control signal comprises NAND gate means.
Claim 5
Dependent Claim
156 words
A memory protect circuit for controlling the writing of data into a data storage unit of a data processing system having a processor for generating an address enable signal to enable an address signal to be applied to a selected storage location of the storage unit and for generating a key code prior to generation of the address enable signal comprising: decode means for receiving the key code and for generating a decoded key code; latch means for receiving said decoded key code and for generating a control signal upon receipt of said decoded key code; means for receiving said control signal and the address enable signal to permit the address enable signal to be applied to the storage unit to allow writing of data into the selected storage location of the storage unit; and said latch means being enabled for each write operation of the processor and disabled following each write operation of the processor.
Claim 6
Dependent Claim
156 words
A memory protect circuit for controlling the writing of data into a data storage unit of a data processing system having a processor for generating an address enable signal to enable an address signal to be applied to a selected storage location of the storage unit and for generating a key code prior to generation of the address enable signal comprising: decode means for receiving the key code and for generating a decoded key code; latch means for receiving said decoded key code and for generating a control signal upon receipt of said decoded key code; means for receiving said control signal and the address enable signal to permit the address enable signal to be applied to the storage unit to allow writing of data into the selected storage location of the storage unit; and said latch means being enabled for each write operation of the processor and disabled following each write operation of the processor.
Claim 7
Dependent Claim
15 words
The memory protect circuit of claim 4 wherein said decode means comprises NOR gate means.
Claim 8
Dependent Claim
53 words
The memory protect circuit of claim 4 and further including: OR gate means for receiving said control signal and for receiving a disable signal generated by the processor to bypass the write protect circuit to enable successive write operations for writing data to the storage unit in the absence of said control signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-05-24 | 1985-11-23 | 1986-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-05-24 | 1989-11-23 | 1990-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-05-24 | 1993-11-23 | 1994-05-25 | $7700.00 | Window Closed / Lapsed |