Digital data processing system having unique addressing means and means for identifying and accessing operands

Claim 1

In a digital computer system including processor means for performing operations upon operands, memory means for storing said operands and instructions for directing said operations, said memory means being organized into objects for containing said operands and said instructions, bus means for conducting operands and instructions between said memory means and said processor means, and input/output (I/O) means for conducting operands between said digital computer system and devices external to said digital computer system, said processor means comprising: arithmetic logic unit (ALU) means connected to said bus means for performing said operations, addressing means connected to said bus means for providing addresses and for controlling the transfer of said operands and instructions between said memory means and said processor means, each of said addresses comprising an object field for identifying a corresponding one of said objects, an offset field for specifying a first number of information bits of offset relative to the start of said corresponding one of said objects, and a length field for specifying a second number of information bits of said corresponding one of said objects following said first number of information bits to be transferred between said memory means and said processor means, and microcode control means for storing sequences of microinstructions for controlling said processor means and responsive to said instructions for providing said sequences of microinstructions to said processor means, said ALU means including general register file means connected to said bus means for storing selected operands and selected addresses, said general register file means comprising a plurality of vertically ordered registers vertically divided into three parallel-operating and addressed parts, a first said part of said general register file means comprising first register file means for storing object fields of said addresses, a second said part of said general register file means comprising second register file means for storing offset fields of said addresses and said selected operands, and a third said part of said general register file means comprising third register file means for storing length fields of said addresses, and address ALU means connected to said general register file means and to said bus means and responsive to first selected sequences of microinstructions for performing operations on said selected addresses, each of said operands being referred to by a corresponding name of a plurality of names and said memory means including name table means for storing name table entries, each of said name table entries corresponding to one of said names and comprising (1) first data resolvable to provide a location in said memory means of an operand referred to by said corresponding name, and, (2) second data resolvable to identify the format of said operand referred to by said corresponding name, said ALU means including means connected to said bus means and responsive to said names for reading said name table entries corresponding to said names from said name table means, and means connected to said reading means for resolving said name table entries and for providing addresses corresponding thereto to said memory means, each said address representing a location in said memory means of the operand referred to by its corresponding name.