Synchronizing circuit for matrix television set

Claim 1

In a synchronizing circuit for a matrix television set having display means including picture elements arranged in a matrix of lines and columns, and connected to line driver and column driver circuits respectively so as to be individually selectable in both line and column directions, and wherein display is made by selecting lines and columns successively, the improvement therein comprising: a voltage controlled oscillator circuit, said oscillator circuit producing a shift clock signal applied to said column driver circuits for selecting individual columns in succession; first frequency divider means for dividing down an output frequency signal from said oscillator circuit, the output of said first frequency divider means being a clock signal applied to said line driver circuits for selecting individual lines in succession; phase comparison means, said comparison means determining the difference in phase of a output of said first frequency divider means with the phase of a horizontal synchronizing signal, said horizontal synchronizing signal being a portion of a television signal transmission, an output of said comparison means being fed back to said oscillator circuit, said feedback being in proportion to said phase difference, said oscillator circuit being adapted to adjust the output frequency of oscillation in response to said phase difference signal, said adjustment causing said phase difference to approach zero, said clock signals being synchronized with said horizontal synchronizing signal; a synchronizing signal separator circuit, said television signal transmission including a composite synchronization signal, said separator circuit separating a vertical synchronizing signal from said composite signal, and a signal including said horizontal synchronizing signal, said synchronizing signal separator circuit including an inverter, first capacitor, first resistor and a MOS FET, said MOS FET having gate and drain electrodes connected together, the source and drain of said MOS FET being connected across said inverter, said first capacitor being connected at one end in series with said inverter and charging through said MOS FET, said signal transmission being input to the other end of said capacitor, said first capacitor discharging through said first resistor.