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US4491958A
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Speech synthesizer
Assignee: Hitachi Ltd
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Filing: 1981-02-17
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Granted: 1985-01-01
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Expires: 2001-02-17
Abstract
Abstract In a speech synthesizer designed so that natural speech is chopped at constant intervals of time and characteristic parameters of the speech are extracted from the chopped speech and used for synthesis of speech, the number of bits of a characteristic parameter per analytical frame is not changed, but the interval of time of one analytical frame is changed to change the amount of information per unit time, while the time interval of one synthesis frame of the synthesizer is changed with the time interval of one analytical frame so that the time interval of one frame upon analysis and the time interval of one frame upon synthesis are made equal, whereby a single speech synthesizer can handle speech parameters of different amounts of information.
Inventors
- 👤 Kazuhiro Umemura
- 👤 Tohru Sampei
- 👤 Kazuo Nakata
- 👤 Hirokazu Sato
- 👤 Murakami Kenya
- 👤 Kiyoshi Intoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:27
CPC Classifications
G; G10; G10L; G10L19/00; G10L19/04; G10L13/00; G10L13/02; G10L13/04; G10L13/047; G10L19/16; G10L19/18; G10L19/24
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
454 words
A speech synthesizer designed to synthesize speech with regard to a selected one of two kinds of speech information whose respective frame periods are different from each other, comprising: a memory for selectively storing one of first speech information including a first plurality of frames having a first frame period and second speech information including a second plurality of frames having a second frame period which is different from the frame period of the frames of said first speech information, each frame of said first and second speech information having a plurality of bits constituting a digital signal including amplitude information, pitch information and PARCOR coefficient which are extracted from a frequency spectrum of a speech signal, the number of bits constituting said digital signal being the same for all frames; a control unit for supplying said memory with a command signal for reading out the speech information stored in said memory; an interface logic for receiving said speech information, from said memory, frame by frame in order and for separating said digital signal into said amplitude information, said pitch information and said parcor coefficient; a counter portion for generating a first synchronizing signal synchronized with the frame period of the frames of said first speech information and a second synchronizing signal synchronized with the frame period of the frames of said second speech information; a switch portion for changing the period of said synchronizing signals of said counter portion in accordance with the frame period of the frames of the speech information stored in said memory; and means for applying the synchronizing signals generated by said counter portion to said interface logic; wherein said counter portion includes a first counter for counting clock pulses to generate a first count output when the number of clock pulses counted thereby reaches a first set count number and to generate a second count output and reset said first counter when the number of clock pulses counted thereby reaches a second set count number that is larger than said first set count numbers, a second counter for counting said second count output to generate a third count output when the number of clock pulses counted thereby reaches a third set count number, a flip-flop which is reset by said first count output and set by said second count output, a logic circuit for forming said synchronizing signals by taking a logic result between a set output of said flip-flop and one of said third count output and a constant voltage from a power supply; and wherein said switch portion selects one of said third count output and the constant voltage from a power supply to be applied to said logic circuit for selection between said synchronizing signals.
Claim 2
Dependent Claim
454 words
A speech synthesizer designed to synthesize speech with regard to a selected one of two kinds of speech information whose respective frame periods are different from each other, comprising: a memory for selectively storing one of first speech information including a first plurality of frames having a first frame period and second speech information including a second plurality of frames having a second frame period which is different from the frame period of the frames of said first speech information, each frame of said first and second speech information having a plurality of bits constituting a digital signal including amplitude information, pitch information and PARCOR coefficient which are extracted from a frequency spectrum of a speech signal, the number of bits constituting said digital signal being the same for all frames; a control unit for supplying said memory with a command signal for reading out the speech information stored in said memory; an interface logic for receiving said speech information, from said memory, frame by frame in order and for separating said digital signal into said amplitude information, said pitch information and said parcor coefficient; a counter portion for generating a first synchronizing signal synchronized with the frame period of the frames of said first speech information and a second synchronizing signal synchronized with the frame period of the frames of said second speech information; a switch portion for changing the period of said synchronizing signals of said counter portion in accordance with the frame period of the frames of the speech information stored in said memory; and means for applying the synchronizing signals generated by said counter portion to said interface logic; wherein said counter portion includes a first counter for counting clock pulses to generate a first count output when the number of clock pulses counted thereby reaches a first set count number and to generate a second count output and reset said first counter when the number of clock pulses counted thereby reaches a second set count number that is larger than said first set count numbers, a second counter for counting said second count output to generate a third count output when the number of clock pulses counted thereby reaches a third set count number, a flip-flop which is reset by said first count output and set by said second count output, a logic circuit for forming said synchronizing signals by taking a logic result between a set output of said flip-flop and one of said third count output and a constant voltage from a power supply; and wherein said switch portion selects one of said third count output and the constant voltage from a power supply to be applied to said logic circuit for selection between said synchronizing signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-01 | 1988-07-02 | 1989-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-01 | 1992-07-02 | 1993-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-01 | 1996-07-02 | 1997-01-01 | $7700.00 | Window Closed / Lapsed |