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PNPN Light sensitive semiconductor switch with phototransistor connected across inner base regions

Assignee: Oki Electric Industry Co Ltd
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Filing: 1981-01-28
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Granted: 1984-12-18
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Expires: 2001-01-28
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Abstract

Abstract A PNPN semiconductor switch including an N type semiconductor substrate, spaced apart first and second P type diffused regions formed on a surface of an N type substrate, spaced apart first and second N type diffused regions formed in the second P type diffused region, a first gate insulating layer formed on the surface of the second P type diffused region between the first and second N type diffused regions to cover portions thereof, a first gate electrode formed on the first gate insulating layer between the first and second N type diffused regions, a resistance region disposed on the first gate insulating layer, one end of the resistance region on the side opposite to the first gate electrode, a second gate insulating layer overlying the first gate electrode and the resistance region, a semiinsulating layer formed on the surface of the substrate except over the first and second P type diffused regions, an insulating layer overlying the semiinsulating layer, a P gate electrode electrically connected to the second P type diffused region and the second N type diffused region, a second gate electrode formed on the second gate insulating layer at a portion above the first gate electrode, a cathode electrode connected to the first N type diffused region, an anode electrode connected to the first P type diffused region and the second gate electrode and a high resistance region formed immediately beneath the first gate insulating layer and between the first and second N type diffused regions.

Inventors

  • 👤 Jun Ueda
  • 👤 Haruo Mori
  • 👤 Kazuo Hagimura
  • 👤 Hirokazu Tsukada
  • 👤 Kotaro Kato

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 20:54
CPC Classifications
H; H10; H10F; H10F30/00; H10F30/20; H10F30/21; H10F30/26; H10F30/263; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/52; H04Q3/521; H10F39/00; H10F39/10; H10F39/103

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 632 words
In a PNPN semiconductor switch of the type comprising: an N type semiconductor substrate; a first P type diffused region formed in said substrate; a second P type diffused region formed in said substrate so as to be spaced apart from said first P type diffused region by a predetermined distance; a first N type diffused region formed in said second P type diffused region; a second N type diffused region formed in said second P type diffused region so as to be spaced apart from said first N type diffused region by a predetermined distance; a first gate insulating layer formed on a surface of said second P type diffused region between said first and second N type diffused regions; a P type gate electrode electrically connected to said second P type diffused region and said second N type diffused region; a first gate electrode of an N type polycrystalline silicon formed on a surface of said first gate insulating layer between said first and second N type diffused regions; a first resistance region of an N type polycrystalline silicon formed so as to extend from said first gate electrode to said P type gate electrode; a second gate insulating layer overlying said first gate electrode; a semiinsulating layer formed on a surface of said substrate except over said first and second P type diffused regions; an insulating layer overlying said semiinsulating layer; a second gate electrode formed on a surface of said second insulating layer over said first gate electrode; a cathode electrode electrically connected to said first N type diffused region; and an anode electrode electrically connected to said first P type diffused region and to said second gate electrode; the improvement which comprises a high resistance region having a low N type impurity concentration formed immediately beneath said first gate insulating layer and between said first and second N type diffused regions, said high resistance region acting a shunt resistor so as to thereby provide a high gate sensitivity for said PNPN semiconductor switch; and further comprising a phototransistor for amplifying a collector current caused by being exposed to light, wherein said phototransistor comprises: a third P type diffused region formed in said substrate so as to be spaced from said second P type diffused region by a predetermined distance; a third N type diffused region formed in said third P type diffused region; a fourth N type diffused region formed in said third P type diffused region so as to be spaced from said third N type diffused region by a predetermined distance; a third gate insulating layer formed on a surface of said third P type diffused region between said third and fourth N type diffused regions; a third gate electrode of an N type polycrystalline silicon formed on a surface of said third gate insulating layer between said third and fourth N type diffused regions; a base electrode electrically connected to said fourth N type diffused region and said third P type diffused region; a second resistance region of an N type polycrystalline silicon formed so as to extend from said third gate electrode to said base electrode; a semiinsulating layer formed on a surface of said substrate except over said second and third P type regions; an emitter electrode electrically connected to said third N type diffused region and to said P gate electrode; a fourth gate insulating layer formed on a surface of said third gate electrode; a fourth gate electrode disposed on a surface of said fourth gate insulating layer over said third gate electrode and electrically connected to said anode electrode; and another high resistance region having a low N type impurity concentration formed immediately beneath said third gate insulating layer and between said third and fourth N type diffused regions.
Claim 2
Dependent Claim 632 words
In a PNPN semiconductor switch of the type comprising: an N type semiconductor substrate; a first P type diffused region formed in said substrate; a second P type diffused region formed in said substrate so as to be spaced apart from said first P type diffused region by a predetermined distance; a first N type diffused region formed in said second P type diffused region; a second N type diffused region formed in said second P type diffused region so as to be spaced apart from said first N type diffused region by a predetermined distance; a first gate insulating layer formed on a surface of said second P type diffused region between said first and second N type diffused regions; a P type gate electrode electrically connected to said second P type diffused region and said second N type diffused region; a first gate electrode of an N type polycrystalline silicon formed on a surface of said first gate insulating layer between said first and second N type diffused regions; a first resistance region of an N type polycrystalline silicon formed so as to extend from said first gate electrode to said P type gate electrode; a second gate insulating layer overlying said first gate electrode; a semiinsulating layer formed on a surface of said substrate except over said first and second P type diffused regions; an insulating layer overlying said semiinsulating layer; a second gate electrode formed on a surface of said second insulating layer over said first gate electrode; a cathode electrode electrically connected to said first N type diffused region; and an anode electrode electrically connected to said first P type diffused region and to said second gate electrode; the improvement which comprises a high resistance region having a low N type impurity concentration formed immediately beneath said first gate insulating layer and between said first and second N type diffused regions, said high resistance region acting a shunt resistor so as to thereby provide a high gate sensitivity for said PNPN semiconductor switch; and further comprising a phototransistor for amplifying a collector current caused by being exposed to light, wherein said phototransistor comprises: a third P type diffused region formed in said substrate so as to be spaced from said second P type diffused region by a predetermined distance; a third N type diffused region formed in said third P type diffused region; a fourth N type diffused region formed in said third P type diffused region so as to be spaced from said third N type diffused region by a predetermined distance; a third gate insulating layer formed on a surface of said third P type diffused region between said third and fourth N type diffused regions; a third gate electrode of an N type polycrystalline silicon formed on a surface of said third gate insulating layer between said third and fourth N type diffused regions; a base electrode electrically connected to said fourth N type diffused region and said third P type diffused region; a second resistance region of an N type polycrystalline silicon formed so as to extend from said third gate electrode to said base electrode; a semiinsulating layer formed on a surface of said substrate except over said second and third P type regions; an emitter electrode electrically connected to said third N type diffused region and to said P gate electrode; a fourth gate insulating layer formed on a surface of said third gate electrode; a fourth gate electrode disposed on a surface of said fourth gate insulating layer over said third gate electrode and electrically connected to said anode electrode; and another high resistance region having a low N type impurity concentration formed immediately beneath said third gate insulating layer and between said third and fourth N type diffused regions.

References Cited (Backward Citations)

US4224634A Cited
US4244000A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-12-18 1988-06-18 1988-12-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-12-18 1992-06-18 1992-12-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-12-18 1996-06-18 1996-12-18 $7700.00 Window Closed / Lapsed

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