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US4488066A
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Databus coupling arrangement using transistors of complementary conductivity type
Assignee: Nokia Bell Labs
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Filing: 1982-11-08
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Granted: 1984-12-11
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Expires: 2002-11-08
Abstract
Abstract To improve the speed of transfer of information to the databus in data processing apparatus, the bus is periodically precharged and the coupling to the databus is by way of a special clocked CMOS buffer circuit.
Inventors
- 👤 Masakazu Shoji
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:53
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072; G06F13/4077; H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018557; H03K5/00; H03K5/01; H03K5/02; H03K5/023
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
171 words
In data processing apparatus, an arrangement for transferring data streams from a plurality of logic networks to a common databus comprising, a databus means under the control of a source of clock pulses for periodically precharging the databus essentially to the potential of one of two power supply terminals, a plurality of logic networks, each for supplying a data stream to be transferred to the databus, and a plurality of coupling networks, one associated with each logic network, each coupling network being connected between the two terminals of the power supply, including an output node for connection to the databus, and supplied with clock pulses and selection pulses whereby the data stream from its associated logic network may be periodically selected for transmission to the databus, characterized in that the coupling network comprises at least one pair of transistors of complementary conductivity type serially connected between the two terminals of the power supply and in that the node between the two transistors is the output node for connection to the databus.
Claim 2
Dependent Claim
171 words
In data processing apparatus, an arrangement for transferring data streams from a plurality of logic networks to a common databus comprising, a databus means under the control of a source of clock pulses for periodically precharging the databus essentially to the potential of one of two power supply terminals, a plurality of logic networks, each for supplying a data stream to be transferred to the databus, and a plurality of coupling networks, one associated with each logic network, each coupling network being connected between the two terminals of the power supply, including an output node for connection to the databus, and supplied with clock pulses and selection pulses whereby the data stream from its associated logic network may be periodically selected for transmission to the databus, characterized in that the coupling network comprises at least one pair of transistors of complementary conductivity type serially connected between the two terminals of the power supply and in that the node between the two transistors is the output node for connection to the databus.
Claim 3
Dependent Claim
53 words
An arrangement in accordance with claim 1 in which the coupling means comprises only a single pair of transistors of complementary conductivity type having their channels connected in series and in which the gates of the two transistors are controlled by the output of the logic network and the clock and selection pulses.
Claim 4
Dependent Claim
45 words
An arrangement in accordance with claim 1 in which the precharging means includes a p-type transistor of relatively large beta and the transistors of complementary conductivity type include a p-type pull-up driver of relatively small beta and an n-type pull-down driver of relatively large beta.
Claim 5
Dependent Claim
68 words
An arrangement in accordance with claim 1 in which the coupling network comprises two pairs of transistors of complementary conductivity type having their channels serially connected, having their gates controlled by the output of the logic network and the clock and selection pulses, and having the node between the two transistors of one type and the two transistors of the opposite type forming the connection to the databus.
Claim 6
Dependent Claim
44 words
An arrangement in accordance with claim 4 in which one of the transistors of each type is under the control of clock pulses and the other of each type is under the control of the output of the logic network and a selection pulse.
Claim 7
Dependent Claim
44 words
An arrangement in accordance with claim 5 in which the precharging means includes a p-type transistor of relatively large beta and the coupling network includes a pair of p-type transistors of relatively small betas and a pair of n-type transistors of relatively large betas.
Claim 8
Dependent Claim
167 words
In data processing apparatus, an arrangement for transferring a stream of data bits to a databus comprising means under the control of a source of clock pulses for periodically precharging the bus to one of two binary states, and a coupling network between the source of the stream of data bits and the databus comprising a first pair of transistors of one conductivity type serially connected and a second pair of transistors of the opposite conductivity type serially connected, the two pairs being serially connected between the first and second terminals of a power supply, the node between the two pairs being electrically connected to the databus, the gates of one transistor of each pair being connected to the source of the stream of data bits, the gate of the other transistor of the first pair being connected to the source of clock pulses and the gate of the other transistor of the second pair being connected to a source of the complement of the clock pulses.
Claim 9
Dependent Claim
167 words
In data processing apparatus, an arrangement for transferring a stream of data bits to a databus comprising means under the control of a source of clock pulses for periodically precharging the bus to one of two binary states, and a coupling network between the source of the stream of data bits and the databus comprising a first pair of transistors of one conductivity type serially connected and a second pair of transistors of the opposite conductivity type serially connected, the two pairs being serially connected between the first and second terminals of a power supply, the node between the two pairs being electrically connected to the databus, the gates of one transistor of each pair being connected to the source of the stream of data bits, the gate of the other transistor of the first pair being connected to the source of clock pulses and the gate of the other transistor of the second pair being connected to a source of the complement of the clock pulses.
Claim 10
Dependent Claim
41 words
The arrangement of claim 7 in which the precharging means includes a fifth transistor whose channel is connected between one of the terminals of the power supply and the databus and whose gate is connected to the source of clock pulses.
Claim 11
Dependent Claim
42 words
The arrangement of claim 7 in which the first pair of transistors are n-type, the second pair are p-type and the fifth transistor is p-type, and the second pair are of relatively small betas compared to the betas of the other transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-11 | 1988-06-11 | 1988-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-11 | 1992-06-11 | 1992-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-11 | 1996-06-11 | 1996-12-11 | $7700.00 | Window Closed / Lapsed |