Snubber circuit for use in an uninterruptible power supply

Claim 2

In an uninterruptible power supply which includes a first source of AC signals and a second source of AC signals, a circuit for regulating the switching of the first and second source of AC signals to the load including: means for generating a first control signal upon sensing the occurrence of a current transient in the output of the second source of AC signals; a source of second control signals generated in response to the failure of the first source of AC signals to supply said AC signals; switching means for connecting the second source of AC signals to the load when enabled; a source of high frequency clock signals; and gate means enabled upon the simultaneous occurrence of said first and second control signals to output said clock signals to said switching means whereby said switching means is operated to cyclically connect said second source of AC signals to the load until the current transient is eliminated.

Claim 3

The circuit of claim 1 which further includes a source of third control signals generated in response to the AC signals of the second source being at zero voltage, said gate means connected to said source of third control signals for outputting said clock signals upon the simultaneous occurrence of said first, second and third control signals.

Claim 4

The circuit of claim 1 which further includes a transformer member connected to said gating means and said switching means and enabled by said clock signals to cyclically operate said switching means in accordance with the frequency of said clock signals.

Claim 5

The circuit of claim 3 in which said second source of AC signals is connected to the load over a two-conductor transmission line, said switching means being connected between said conductors to cyclically apply the AC signals from the second source to the load when enabled.

Claim 6

The circuit of claim 4 in which said switching means comprises a MOSFET having its drain electrode connected to one of the conductors and its source electrode connected to the other conductor, said power supply further including a plurality of unidirectional members connected between the conductors whereby the transistor transmits one portion of the AC signal applied to the conductors and the unidirectional members transmit the remaining portion of the AC signals enabling the AC signals to be cyclically applied to the load.

Claim 7

In an uninterruptible power supply for supplying AC signals to a load which includes a source of AC signals and an inverter for supplying AC signals from a DC source, a circuit for regulating switching current transient generated in switching the inverter to the load including: logic circuit means for generating a first control signal upon sensing the occurrence of a current transient in the AC output of the inverter; a source of second control signals generated in response to the failure of the source to supply AC signals to the load; transistor means connected to the output of the inverter and the load for connecting the output of the inverter to the load when enabled; a drive transformer connected to said transistor means for enabling said transistor means when operated; a source of first and second high frequency clock signals; and control means enabled upon the simultaneous occurrence of said first and second control signals to output the clock signals to said drive transformer to cyclically operate said drive transformer whereby said transistor is cyclically enabled to connect the output of the inverter to the load until the current transient is eliminated.

Claim 8

In an uninterruptible power supply for supplying AC signals to a load which includes a source of AC signals and an inverter for supplying AC signals from a DC source, a circuit for regulating switching current transient generated in switching the inverter to the load including: logic circuit means for generating a first control signal upon sensing the occurrence of a current transient in the AC output of the inverter; a source of second control signals generated in response to the failure of the source to supply AC signals to the load; transistor means connected to the output of the inverter and the load for connecting the output of the inverter to the load when enabled; a drive transformer connected to said transistor means for enabling said transistor means when operated; a source of first and second high frequency clock signals; and control means enabled upon the simultaneous occurrence of said first and second control signals to output the clock signals to said drive transformer to cyclically operate said drive transformer whereby said transistor is cyclically enabled to connect the output of the inverter to the load until the current transient is eliminated.

Claim 9

The circuit of claim 6 which further includes a source of third control signals generated at the time the inverter is not outputting an AC signal, said source of third control signals being connected to said control means whereby said control means outputs the clock signals to said transformer upon the simultaneous occurrence of said first, second and third control signals.

Claim 10

The circuit of claim 7 which further includes a two-wire transmission line interconnecting the inverter and the load, said transistor means being connected across said wires to cyclically apply the AC signals received from the inverter to the load when enabled.

Claim 11

The circuit of claim 8 in which said transistor means comprises a metal oxide semiconductor field effect transistor having its gate electrode connected to said transformer, its drain electrode connected to one of the transmission wires and its source electrode connected to the other wire of said transmission line, said power supply further including a plurality of first diodes connected between the wires of the transmission line and a plurality of second diodes connected between the wires of the transmission line in a direction opposite to said first diodes whereby the transistor will transmit one portion of the AC signal to the load and the first and second diodes transmitting the remaining portion of the AC signal to the load.

Claim 12

The circuit of claim 7 which further includes a source of reference AC signals and the output AC signals of the inverter, said logic circuit means includes a comparator receiving said reference AC signals and the output AC signals of the inverter for outputting said first control signal when the output of the AC signals exceeds the reference AC signals.

Claim 13

The circuit of claim 8 in which said control means includes a first NAND gate receiving said first clock signals and said first and third control signals, said control means further includes drive means connected to the output of said NAND gate and said transformer and enabled by said second control means for driving said transformer in response to receiving said first clock signals whereby said transistor means is enabled in accordance with the frequency rate of said clock signals.

Claim 14

The circuit of claim 11 in which the frequency rate of said clock signals is 50 KHz.

Claim 15

The circuit of claim 11 in which said drive means include a first drive circuit connected to the output of said NAND gate and said transformer for transmitting the output of said NAND gate to the transformer when enabled and a second drive circuit connected to said first drive circuit and the source of said second control signals for enabling said first drive circuit upon the generation of a second control signal.

Claim 16

The circuit of claim 13 in which said drive transformer includes primary windings having one end connected to said first drive circuit, said control means further includes a second NAND gate receiving said second clock signals and said first and third control signals for outputting said second clock signals upon the simultaneous occurrence of said first and third control signals, and a third drive circuit connected to the output of said second NAND gate and said primary windings and enabled by the operation of said second drive circuit to output said second clock signals to the transformer whereby the transistor means is enabled at the frequency rate of said first and second clock signals.