Electronic identification system

Claim 2

An electronic identification system comprising: a moveable part having a preprogrammed passive memory array containing an electronic identification code, and a readible memory connected to said passive memory array and having its output fed back to its input, and a fixed part capable of being coupled with the moveable part and comprising electric power supply means for supplying electric power, electronic means for supplying a pulse to said moveable part thereby causing the electronic identification code to be loaded into the readible memory of the said moveable part, a fixed part memory, said electronic means for reading the contents of the readible memory of the moveable part and transferring them into said fixed part memory and comparison means for comparison with a code preprogrammed into the said fixed part, wherein said electronic means transmits, before the reading operation, a set number of preliminary clock pulses, which is different from a multiple of the number of bits in the said readible memory and which each time leads to a permutation of its contents, and a logic gate for enabling transfer of the contents of said readible memory to the fixed part memory for reading only after transmission of the set number of preliminary pulses.

Claim 3

The identification system according to claim 1, characterized in that the moveable part comprises control means for counting said set number of successive preliminary clock pulses and wherein said logic gate is connected to the output of said readible memory and to the output of said control means so as to enable transfer of the contents of the moveable part readible memory to said fixed part memory in the fixed part only after said set number of clock pulses.

Claim 4

The identification system according to claim 1, characterized in that the fixed part comprises a clock modulation circuit for counting said set number of preliminary clock pulses transmitted by the said electronic means, with the said modulation circuit being linked to a read stop circuit so as to additionally enable the transmission of an additional number of read pulses equal to the number of bits in the readible memory of the moveable part subsequent to said set number of preliminary clock pulses.

Claim 5

The identification system according to claim 3, characterized in that the clock modulation circuit and the control means comprise a set of counters associated with one or more logic gates.

Claim 6

The identification system according to claim 1 characterized in that the said electronic means for transmitting a loading pulse comprise a loading circuit provided with a master-slave type double flip-flop associated with a NAND gate and a clock supplying loading pulses to said double flip-flop and said NAND gate.

Claim 7

The identification system according to claim 1, characterized in that the electronic means for reading the contents of the readible memory of the moveable part comprise a clock, a reading circuit provided with a second master-slave type double flip-flop associated with a second NAND gate receiving the pulses from said clock and connected to the output of said electronic means supplying the loading pulse in such a way as to supply successive read pulses.

Claim 8

The identification system according to claim 1, characterized in that the electronic means of the fixed part also comprises a read stop circuit provided with at least one pulse counter and a monostable multivibrator connected to the output of the reading means and capable of delivering a read stop pulse when the contents of the moveable part readible memory have been read once.

Claim 9

The identification system according to claim 1, characterized in that the memory array in the moveable part comprises a plurality of switches whose positions determine said electronic identification code and said readable memory comprises a plurality of flip-flops wherein each said flip-flop is connected via two NAND gates with one of the switches whose position controls the state of the connected flip-flop, with one common input of both gates receiving said loading pulse and with the first of the said gates being connected by its other input to the switch and with the second gate receiving the output from the first gate on its other input.

Claim 10

The identification system according to claim 1, characterized in that it also comprises an alarm and a successive tests enabling circuit connected to the alarm and provided with a succession of flip-flops which are reset to zero when said comparison means tests for and successfully determines equivalence between said electronic identification code and the code preprogrammed into the fixed part so that when a number of unsuccessful tests performed by said comparison means equals the number of flip-flops of the said succession of flip-flops, said alarm is thereby triggered.

Claim 11

The identification system according to claim 1, characterized in that said fixed part memory comprises system resettable memory and said system also comprises first timing means connected to a monostable multivibrator for resetting all the system's resettable memory after the moveable part has been coupled with the fixed part and before transmission of the loading pulse.

Claim 12

The identification system according to claim 10, characterized in that it also comprises second timing means connected to a set of monostable multivibrators for resetting all the system's resettable memory and cutting off the power supply of the fixed part after the moveable part has been uncoupled from the fixed part.

Claim 13

An electronic identification system comprising a fixed electronic receptacle and a portable electronic key adapted to be inserted into a portion of said receptacle and thereby electrically connected thereto, said portable electronic key comprising a clockable multiple stage internal shift register configured as a recirculating ring counter which is provided with an initial predetermined bit pattern and which has a common clocking input connection and a serial bit stream output connection, each being connectable to said receptacle, said electronic receptacle comprising: initialization means for initializing said system when said key becomes electrically connected to said receptacle, clock pulse generation means responsive to said initialization means for generating and putting out to said key at least two clock pulse groups including an initial group and a read group during a subsequent read interval, wherein said initial pulse group is not a multiple of the number of stages of said shift register so that after said initial pulse group has been applied thereto the bit pattern thereof has permuted, and wherein said read group is equal to the number of stages of said shift register and causes it to put out said permuted bit pattern thereof to said receptacle, electronic memory means connected to receive as serial bits and store said permuted bit pattern from said shift register during said read interval, preprogrammed array means for providing a bit pattern predetermined to correspond to a valid permuted bit pattern stored in said electronic memory means during said read interval, comparator means connected to said electronic memory means and to said preprogrammed array means for comparing the bit pattern stored in said memory means with said predetermined array bit pattern to determine equivalence or non-equivalence, and system identification confirmation output means connected to said comparator means and responsive to determined equivalence in said comparator means.

Claim 14

An electronic identification system comprising a fixed electronic receptacle and a portable electronic key adapted to be inserted into a portion of said receptacle and thereby electrically connected thereto, said portable electronic key comprising a clockable multiple stage internal shift register configured as a recirculating ring counter which is provided with an initial predetermined bit pattern and which has a common clocking input connection and a serial bit stream output connection, each being connectable to said receptacle, said electronic receptacle comprising: initialization means for initializing said system when said key becomes electrically connected to said receptacle, clock pulse generation means responsive to said initialization means for generating and putting out to said key at least two clock pulse groups including an initial group and a read group during a subsequent read interval, wherein said initial pulse group is not a multiple of the number of stages of said shift register so that after said initial pulse group has been applied thereto the bit pattern thereof has permuted, and wherein said read group is equal to the number of stages of said shift register and causes it to put out said permuted bit pattern thereof to said receptacle, electronic memory means connected to receive as serial bits and store said permuted bit pattern from said shift register during said read interval, preprogrammed array means for providing a bit pattern predetermined to correspond to a valid permuted bit pattern stored in said electronic memory means during said read interval, comparator means connected to said electronic memory means and to said preprogrammed array means for comparing the bit pattern stored in said memory means with said predetermined array bit pattern to determine equivalence or non-equivalence, and system identification confirmation output means connected to said comparator means and responsive to determined equivalence in said comparator means.

Claim 15

The identification system set forth in claim 12 wherein said shift register of said key comprises a series of tandem-connected flip-flops connected into a ring counter, a series of bit switches each connected to a flip-flop and arrayed to provide said initial predetermined bit pattern and wherein said initialization circuit functions to load said initial predetermined bit pattern into said flip-flops.

Claim 16

The identification system set forth in claim 12 wherein said key further comprises counter means connected to receive said initial group of pulses from said clock means, and gate means connected and enabled by said counter means to pass said serial stream permuted bit pattern to said memory means for storage therein.

Claim 17

The identification system set forth in claim 12 further comprising in said receptacle a successive tests enabling circuit comprising test repetition means for successively storing and comparing said serial stream permuted bit pattern and a succession of flip-flops which are reset to zero by the determination of equivalence by said comparator means and which are incremented successively by the determination of non-equivalence by said comparator means, and alarm means connected to respond to said flip-flops when the last thereof becomes incremented.