Patent US4485355A successfully refreshed from Google Patents.
US4485355A
Expired / Lapsed
US
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Switched geometry oscillator
Assignee: Texas Instruments Inc
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Filing: 1982-02-02
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Granted: 1984-11-27
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Expires: 2002-02-02
Abstract
Abstract A very simple oscillator circuit, using a FET pair with RF coupled, DC isolated gates, selectively operates at two widely separated microwave frequencies. The two FETs are DC isolated so that one of them can be pinched off (to act as a passive element) while the other remains active. Thus, for example, a two-FET push-push oscillator operating at 20 GHz can switch downband, when one FET is pinched off, to act as a fundamental mode oscillator at 121/2 GHz. The circuit is integrable. In alternative embodiments, more than two FETs are used, for switching over a wider frequency range when one or two of them is pinched off.
Inventors
- 👤 Bentley N. Scott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:45
CPC Classifications
H; H03; H03B; H03B5/00; H03B5/18; H03B5/1841; H03B5/1847; H03B5/1852; H03B2200/00; H03B2200/003; H03B2200/0048; H03B2200/006; H03B2200/0098
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
99 words
An oscillator comprising: a plurality of transistors, each said transistor comprising a gate, a source, and a drain, said respective sources of all of said transistors being electrically common, and said respective drains of all of said transistors being electrically common, and at least one of said respective gates being RF-coupled to and DC-isolated from the others of said respective gates; means, connected to at least one of said gates, for selectably biasing at least one but less than all of said transistors to pinch-off; and frequency determining electrical reactance means connected to at least one of said gates.
Claim 2
Dependent Claim
99 words
An oscillator comprising: a plurality of transistors, each said transistor comprising a gate, a source, and a drain, said respective sources of all of said transistors being electrically common, and said respective drains of all of said transistors being electrically common, and at least one of said respective gates being RF-coupled to and DC-isolated from the others of said respective gates; means, connected to at least one of said gates, for selectably biasing at least one but less than all of said transistors to pinch-off; and frequency determining electrical reactance means connected to at least one of said gates.
Claim 3
Dependent Claim
35 words
The oscillator of claim 1, wherein an inductive reactance means is interposed between said respective gates, whereby voltages on said gates are out of phase when said selective pinch-off means has not pinched-off said gates.
Claim 4
Dependent Claim
31 words
The oscillator of claim 2 comprising only two of said transistors, the respective voltages on said respective gates being 180 degrees out of phase when both said transistors are not pinched-off.
Claim 5
Dependent Claim
24 words
The oscillator of claim 1 wherein a respective large capacitance means is interposed between respective ones of said gates, whereby said gates are DC-isolated.
Claim 6
Dependent Claim
31 words
The oscillator of claim 4, wherein each said respective gate is directly connected to said respective capacitance means, and further comprising: an inductive reactance means interposed between said gates and ground.
Claim 7
Dependent Claim
28 words
The oscillator of claim 5, wherein at least one of said transistors comprises a gate length which is unequal to the gate length of others of said transistors.
Claim 8
Dependent Claim
13 words
The oscillator of claim 5, wherein said oscillator comprises three of said transistors.
Claim 9
Dependent Claim
19 words
The oscillator of claim 7, wherein said three transistors comprise respective gate lengths in the approximate ratio of 1:2:6.
Claim 10
Dependent Claim
20 words
The oscillator of claim 1, 2, 3, 4, 5, 6, 7, or 8, wherein each said transistor is a MESFET.
Claim 11
Dependent Claim
14 words
The oscillator of claim 9, wherein each said transistor comprises a GaAs channel region.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-27 | 1988-05-28 | 1988-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-27 | 1992-05-28 | 1992-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-27 | 1996-05-28 | 1996-11-27 | $7700.00 | Window Closed / Lapsed |