Circuit arrangement for suppressing outgoing-signal noises in system for bidirectional transmission of digitized signals over two-wire line

Claim 1

In a telephone station having an outgoing branch provided with a signal transmitter and an incoming branch provided with a signal receiver connected via a duplexing terminal to a two-wire line for exchanging voice samples with a remote communicator, said voice samples being digitized with a three-level bipolar NRZI-type code, the combination therewith of a circuit arrangement for suppressing in said incoming branch noises due to outgoing voice samples imperfectly balanced out by said duplexing terminal, comprising: timing means controlling the conversion of voice samples generated by said transmitter into code words with a multiplicity of three-level bits traversing said outgoing branch in successive bit periods of a time slot assigned to a code word; a shift register with n stages in said outgoing branch controlled by said timing means for containing up to n three-level bits in respective stages during each bit period; a random-access memory with address inputs connected to said stages and with 2 n+1 cells addressable by as many combinations of three-level bits in said input and a data output for loading an addressed cell in response to a writing command and extracting the contents thereof in response to a reading commend from said timing means; and arithmetic means in said incoming branch controlled by said timing means and connected to said data output and to said data input for comparing the contents of an addressed cell during a reading phase of a bit period with a noise signal from said duplexing terminal due to a concurrently transmitted voice sample and for deriving from the result of comparison a corrective signal entered in the same cell during a writing phase of such bit period, said arithmetic means including a subtractor delivering to said receiver a purged sample corresponding to the difference between a noise-contaminated incoming voice sample and said corrective signal, said subtractor having respective inputs connected to said data output and to said duplexing terminal, said arithmetic means further comprising an algebraic adder having a first input connected in parallel with said receiver to an output of said subtractor for receiving an updating signal derived from said purged sample and having a second input connected to said data output, said adder having an output connected to said data input, said timing means comprising a clock circuit responsive to synchronizing bits accompanying incoming voice samples, said clock circuit generating timing pulses controlling at least the loading of said adder with said updating signal during a reading phase of a bit period.