Patent US4484299A successfully refreshed from Google Patents.
US4484299A
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Digital filter arrangement having memory means with addressable words stored therein
Assignee: STC PLC
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Filing: 1982-03-09
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Granted: 1984-11-20
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Expires: 2002-03-09
Abstract
Abstract A digital filter arrangement in which an input pulse stream is entered in consecutive non-overlapping groups into a first shift register. The contents of the first register are transferred in parallel into a plurality of shift registers. Bits are read-out from selected positions of the plurality of shift registers to form address words for individual read-only memories (ROM). Each ROM has stored therein weighted impulse response outputs which are read out in accordance with the address words. The outputs from the ROM's are added in logic circuitry and the combined output is fed into a latch. The contents of the latch are entered into a buffer from where they are read out serially. If the input clock rate is 28 MHz and the plurality of shift registers number eight, the plurality of shift registers, the ROM's and the logic circuitry operate at 3.5 MHz.
Inventors
- 👤 Edward H. Lambourn
- 👤 Gideon A. Senensieb
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:54
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/06; H03H17/0607
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
205 words
A digital filter arrangement for a serial pulse stream having a given clock rate comprising: a plurality of shift registers operating in parallel, each of said shift registers having pulses read out in parallel from selected positions thereof, predetermined combinations of said pulses read out of said plurality of shift registers providing a plurality of address words; first means coupled to said plurality of shift registers to distribute individual pulses of groups of pulses of said pulse stream into different ones of said plurality of shift registers sequentially and cyclically to produce said plurality of address words; addressable memory means coupled to said plurality of shift registers, said memory means having a plurality of storage locations each having stored therein a digital word, said memory means providing in a non-volatile manner said digital word of each of said plurality of storage locations in response to associated ones of said plurality of address words; second means coupled to said memory means to sum said digital words read out of said plurality of storage locations; and logic means coupled to said second means for providing a serial output for said filter arrangement from said sum of said digital words read out of said plurality of storage locations.
Claim 2
Dependent Claim
205 words
A digital filter arrangement for a serial pulse stream having a given clock rate comprising: a plurality of shift registers operating in parallel, each of said shift registers having pulses read out in parallel from selected positions thereof, predetermined combinations of said pulses read out of said plurality of shift registers providing a plurality of address words; first means coupled to said plurality of shift registers to distribute individual pulses of groups of pulses of said pulse stream into different ones of said plurality of shift registers sequentially and cyclically to produce said plurality of address words; addressable memory means coupled to said plurality of shift registers, said memory means having a plurality of storage locations each having stored therein a digital word, said memory means providing in a non-volatile manner said digital word of each of said plurality of storage locations in response to associated ones of said plurality of address words; second means coupled to said memory means to sum said digital words read out of said plurality of storage locations; and logic means coupled to said second means for providing a serial output for said filter arrangement from said sum of said digital words read out of said plurality of storage locations.
Claim 3
Dependent Claim
75 words
An arrangement according to claim 1, wherein said memory means includes a plurality of separate memories, one for each of said shift registers, each of said memories having a number of storage locations addressable by address words only from the associated one of said plurality of shift registers, and said adder means includes second means for adding said digital words read out of all of said memories once for each cycle of said serial output.
Claim 4
Dependent Claim
15 words
An arrangement according to claim 2, wherein each of said memories is a read-only memory.
Claim 5
Dependent Claim
31 words
An arrangement according to claims 1, 2 or 3, wherein said pulses read out of said plurality of shift registers are read from corresponding positions in each of said shift registers.
Claim 6
Dependent Claim
81 words
An arrangement according to claim 4, wherein said first means includes an input shift register having one pulse position for each of said shift registers of said plurality of shift registers, and third means to transfer the contents of each pulse position of said input shift register in parallel to associated ones of said shift registers of said plurality of shift registers after each consecutive non-overlapping group of pulses of said pulse stream has been entered into said input shift register.
Claim 7
Dependent Claim
45 words
An arrangement according to claim 5, further including means to shift pulses in said plurality of shift registers therethrough at a clock rate equal to 1/n times said pulse stream clock rate, where n is equal to the number of said plurality of shift registers.
Claim 8
Dependent Claim
36 words
An arrangement according to claim 6, wherein said pulses read out of said plurality of shift registers are read from equally spaced selected positions in each of said shift registers of said plurality of shift registers.
Claim 9
Dependent Claim
28 words
An arrangement according to claim 7, wherein said selected positions include the first and last position of each of said shift registers of said plurality of shift registers.
Claim 10
Dependent Claim
45 words
An arrangement according to claim 4, further including means to shift pulses in said plurality of shift registers therethrough at a clock rate equal to 1/n times said pulse stream clock rate, where n is equal to the number of said plurality of shift registers.
Claim 11
Dependent Claim
30 words
An arrangement according to claim 9, wherein said pulses read out of said plurality of shift registers are read from equally spaced selected positions in each of said shift registers.
Claim 12
Dependent Claim
22 words
An arrangement according to claim 10, wherein said selected positions include the first and last position of each of said shift registers.
Claim 13
Dependent Claim
30 words
An arrangement according to claim 4, wherein said pulses read out of said plurality of shift registers are read from equally spaced selected positions in each of said shift registers.
Claim 14
Dependent Claim
22 words
An arrangement according to claim 12, wherein said selected positions include the first and last position of each of said shift registers.
Claim 15
Dependent Claim
84 words
An arrangement according to claims 1, 2 or 3, wherein said first means includes an input shift register having one pulse position for each of said shift registers of said plurality of shift registers, and third means to transfer the contents of each pulse position of said input shift register in parallel to associated ones of said shift registers of said plurality of shift registers after each consecutive non-overlapping group of pulses of said pulse stream has been entered into said input shift register.
Claim 16
Dependent Claim
45 words
An arrangement according to claim 14, further including means to shift pulses in said plurality of shift registers therethrough at a clock rate equal to 1/n times said pulse stream clock rate, where n is equal to the number of said plurality of shift registers.
Claim 17
Dependent Claim
36 words
An arrangement according to claim 15, wherein said pulses read out of said plurality of shift registers are read from equally spaced selected positions in each of said shift registers of said plurality of shift registers.
Claim 18
Dependent Claim
28 words
An arrangement according to claim 16, wherein said selected positions include the first and last position of each of said shift registers of said plurality of shift registers.
Claim 19
Dependent Claim
48 words
An arrangement according to claims 1, 2 or 3, further including means to shift pulses in said plurality of shift registers therethrough at a clock rate equal to 1/n times said pulse stream clock rate, where n is equal to the number of said plurality of shift registers.
Claim 20
Dependent Claim
30 words
An arrangement according to claim 18, wherein said pulses read out of said plurality of shift registers are read from equally spaced selected positions in each of said shift registers.
Claim 21
Dependent Claim
22 words
An arrangement according to claim 19, wherein said selected positions include the first and last position of each of said shift registers.
Claim 22
Dependent Claim
33 words
An arrangement according to claims 1, 2 or 3, wherein said pulses read out of said plurality of shift registers are read from equally spaced selected positions in each of said shift registers.
Claim 23
Dependent Claim
22 words
An arrangement according to claim 21, wherein said selected positions include the first and last position of each of said shift registers.
Claim 24
Independent Claim
96 words
A method of filtering a serial digital pulse stream comprising the steps of distributing pulses of said pulse stream sequentially and cyclically to a plurality of shift registers operating in parallel; forming address words from pulses read out in parallel from selected positions in each of said shift registers; reading contents of each storage location of an addressable memory in response to an associated one of said address words for each storage location; summing said contents read out of said storage locations; and serially outputting said sum of said contents read out of said storage locations.
Claim 25
Independent Claim
96 words
A method of filtering a serial digital pulse stream comprising the steps of distributing pulses of said pulse stream sequentially and cyclically to a plurality of shift registers operating in parallel; forming address words from pulses read out in parallel from selected positions in each of said shift registers; reading contents of each storage location of an addressable memory in response to an associated one of said address words for each storage location; summing said contents read out of said storage locations; and serially outputting said sum of said contents read out of said storage locations.
References Cited (Backward Citations)
US4146931A
Cited
US4374426A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-20 | 1988-05-21 | 1988-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-20 | 1992-05-21 | 1992-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-20 | 1996-05-21 | 1996-11-20 | $7700.00 | Window Closed / Lapsed |