Binary weighted resistor and package

Claim 2

A binary weighted resistance comprising: a substrate; a thin film resistance formed on said substrate and having an input terminal, an output terminal and a plurality of discrete portions, each portion having a specified impedance such that said specified impedances relate to one another in a binary sequence; a lead frame having pin connections for connecting corresponding ones of said plurality of discrete portions such that a first series circuit from said input terminal through said plurality discrete portions to said output terminal is formed; shunt links on said lead frame connected between corresponding ones of said pin connections such that a second series circuit from said input terminal to said output terminal is formed parallel to said first series circuit; and a plastic housing encapsulating said substrate, said thin film resistance and a portion of said lead frame, such that said input terminal and said output terminal and said shunt links are external to said housing to permit selective removal of said shunt links to interrupt said second series circuit for external control of said binary sequency of said discrete portions.

Claim 3

A binary selectable resistor comprising: a substrate; a thin film resistance formed on said substrate having a predetermined plurality of distinct areas of varied impedance in a binary sequence segregated about the periphery of the substrate; a lead frame encircling said substrate including leads to each of said distinct areas, an input terminal and an output terminal, peripheral shunt links connected so as to form bypassing conductive paths about corresponding ones of said distinct areas and to form a circuit about said periphery of the substrate in parallel with said thin film resistance, said shunt links being severable selectively from said lead frame to provide an impedance value of a desired binary sequence between said input and output terminals; and means for encapsulating said substrate, said thin film resistance and a portion of said lead frame, for providing peripheral, protected access to said shunt links of said lead frame and for enabling removal of selected shunt links to modify an impedance value between said input and output terminals after encapsulation and without penetration of the encapsulation.

Claim 4

A binary selectable resistor comprising: a substrate; a thin film resistance formed on said substrate having a predetermined plurality of distinct areas of varied impedance in a binary sequence segregated about the periphery of the substrate; a lead frame encircling said substrate including leads to each of said distinct areas, an input terminal and an output terminal, peripheral shunt links connected so as to form bypassing conductive paths about corresponding ones of said distinct areas and to form a circuit about said periphery of the substrate in parallel with said thin film resistance, said shunt links being severable selectively from said lead frame to provide an impedance value of a desired binary sequence between said input and output terminals; and means for encapsulating said substrate, said thin film resistance and a portion of said lead frame, for providing peripheral, protected access to said shunt links of said lead frame and for enabling removal of selected shunt links to modify an impedance value between said input and output terminals after encapsulation and without penetration of the encapsulation.

Claim 5

A resistor chip having an impedance variable in accordance with a binary sequence comprising: a substrate; a resistive element formed on said substrate, said resistive element having selected areas of differing impedence related to each other in accordance with said binary sequence; a lead frame including leads connected to corresponding ones of said selected areas, and shunt links connected between corresponding ones of said leads to provide respective by-pass circuits in parallel with each of said areas, said shunt links being selectively removable to vary said impedance in accordance with said binary sequence; and housing means for protecting said substrate, said resistive element and a portion of said lead frame, such that respective portions of said input terminal, of said output terminal and of said lead frame are external to said housing means, and for providing protected, peripheral exposure of said shunt links to enable variation of said impedance of said resistor chip.

Claim 6

A resistor chip having an impedance variable in accordance with a binary sequence comprising: a substrate; a resistive element formed on said substrate, said resistive element having selected areas of differing impedence related to each other in accordance with said binary sequence; a lead frame including leads connected to corresponding ones of said selected areas, and shunt links connected between corresponding ones of said leads to provide respective by-pass circuits in parallel with each of said areas, said shunt links being selectively removable to vary said impedance in accordance with said binary sequence; and housing means for protecting said substrate, said resistive element and a portion of said lead frame, such that respective portions of said input terminal, of said output terminal and of said lead frame are external to said housing means, and for providing protected, peripheral exposure of said shunt links to enable variation of said impedance of said resistor chip.

Claim 7

A chip comprising: a substrate; a plurality of circuit devices on said substrate related to each other in a predetermined sequence; a lead frame positioned about said substrate and including an input and an output terminal, each operatively connected to respective ones of said plurality of devices; a plurality of connections, each connected to a corresponding one of said plurality of circuit devices; peripherally located, severable conductive links, each link operatively connected between corresponding ones of said connections to each of said plurality of circuit devices to shunt said connections and to connect said input and said output terminals; and encapsulating means for encapsulating said substrate, said plurality of circuit devices and portions of said lead frame such that portions of said input and output terminals and each of said conductive links are external to said encapsulating means, each of said conductive links being removable adjacent the periphery of the encapsulating means to interrupt the shunt between said corresponding ones of said connections, to connect said corresponding circuit device in series with said input and output terminals of said lead frame.

Claim 8

A chip comprising: a substrate; a plurality of circuit devices on said substrate related to each other in a predetermined sequence; a lead frame positioned about said substrate and including an input and an output terminal, each operatively connected to respective ones of said plurality of devices; a plurality of connections, each connected to a corresponding one of said plurality of circuit devices; peripherally located, severable conductive links, each link operatively connected between corresponding ones of said connections to each of said plurality of circuit devices to shunt said connections and to connect said input and said output terminals; and encapsulating means for encapsulating said substrate, said plurality of circuit devices and portions of said lead frame such that portions of said input and output terminals and each of said conductive links are external to said encapsulating means, each of said conductive links being removable adjacent the periphery of the encapsulating means to interrupt the shunt between said corresponding ones of said connections, to connect said corresponding circuit device in series with said input and output terminals of said lead frame.