US4484088A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS Four-transistor reset/set latch
Assignee: General Electric Co
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Filing: 1983-02-04
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Granted: 1984-11-20
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Expires: 2003-02-04
Abstract
Abstract An R/S latch circuit employing four IGFETs, one pair of P-channel IGFETs, and another pair of N-channel IGFETs. The P-channel IGFETs have channels respectively connecting Q and &upbar& Q data output nodes to +VDD, and gates cross-connected to the opposite data output nodes. The N-channel IGFETs have channels respectively connecting the Q and &upbar& Q data output nodes to ground, and have gates which respectively comprise the Reset (R) and Set (S) data inputs. A pair of high impedance leakage current paths may also be provided respectively electrically connecting the Q and &upbar& Q data output nodes to ground. Particular integrated circuit R/S latch structures are disclosed.
Inventors
- 👤 Moshe Mazin
- 👤 William E. Engeler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:02
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
452 words
In an integrated circuit device formed on a semiconductor substrate, a Reset/Set latch comprising: a pair of voltage supply nodes; a first pair of insulated-gate field-effect transistors of one channel conductivity type, each transistor of said first pair of transistors including a source region and a drain region of the one conductivity type formed within the substrate, and including an insulated gate electrode on the substrate configured for inducing a conduction channel between said source region and said drain region of each of said first transistor pair, said source regions of said first transistor pair electrically connected to each other and to one of said pair of voltage supply nodes, said gate electrode of one transistor of said first transistor pair being electrically connected to said drain region of the other transistor of said first transistor pair, said gate electrode of said other of said first transistor pair being electrically connected to said drain region of said one of said first transistor pair, and said drain regions of said first transistor pair respectively defining first and second complementary data output nodes; a second pair of insulated-gate field-effect transistors of opposite channel conductivity type, each of said second pair of transistors including a source region and a drain region of the opposite conductivity type formed within the substrate, and including an insulated gate electrode on the substrate configured for inducing a conduction channel between said source region and said drain region of said second transistor pair, said gate electrodes of said second transistor pair respectively defining first and second data input nodes, said source regions of said second transistor pair electrically connected to each other and to the other of said pair of voltage supply nodes, and said drain regions of said second transistor pair respectively electrically connected to respective drain regions of said first transistor pair; each of said transistors of said second pair being formed within its own well region of the one conductivity type; a pair of ohmic contacts between said well regions and said other voltage supply node, each of said ohmic contacts including a heavily-doped contact region of the one conductivity type at a surface of the substrate and adjoining the respective well region; a pair of depletion-mode field-effect transistors of said opposite channel conductivity type, each having an implanted channel region of the opposite conductivity type formed in said semiconductor substrate, said source regions of said second transistor pair respectively serving as source regions of said depletion-mode transistors, said drain regions of said second transistor pair respectively serving as drain regions of said depletion-mode transistors, and the gate of each said depletion-mode transistors connected to the gate of a respective one of said second pair of transistors.
Claim 2
Dependent Claim
452 words
In an integrated circuit device formed on a semiconductor substrate, a Reset/Set latch comprising: a pair of voltage supply nodes; a first pair of insulated-gate field-effect transistors of one channel conductivity type, each transistor of said first pair of transistors including a source region and a drain region of the one conductivity type formed within the substrate, and including an insulated gate electrode on the substrate configured for inducing a conduction channel between said source region and said drain region of each of said first transistor pair, said source regions of said first transistor pair electrically connected to each other and to one of said pair of voltage supply nodes, said gate electrode of one transistor of said first transistor pair being electrically connected to said drain region of the other transistor of said first transistor pair, said gate electrode of said other of said first transistor pair being electrically connected to said drain region of said one of said first transistor pair, and said drain regions of said first transistor pair respectively defining first and second complementary data output nodes; a second pair of insulated-gate field-effect transistors of opposite channel conductivity type, each of said second pair of transistors including a source region and a drain region of the opposite conductivity type formed within the substrate, and including an insulated gate electrode on the substrate configured for inducing a conduction channel between said source region and said drain region of said second transistor pair, said gate electrodes of said second transistor pair respectively defining first and second data input nodes, said source regions of said second transistor pair electrically connected to each other and to the other of said pair of voltage supply nodes, and said drain regions of said second transistor pair respectively electrically connected to respective drain regions of said first transistor pair; each of said transistors of said second pair being formed within its own well region of the one conductivity type; a pair of ohmic contacts between said well regions and said other voltage supply node, each of said ohmic contacts including a heavily-doped contact region of the one conductivity type at a surface of the substrate and adjoining the respective well region; a pair of depletion-mode field-effect transistors of said opposite channel conductivity type, each having an implanted channel region of the opposite conductivity type formed in said semiconductor substrate, said source regions of said second transistor pair respectively serving as source regions of said depletion-mode transistors, said drain regions of said second transistor pair respectively serving as drain regions of said depletion-mode transistors, and the gate of each said depletion-mode transistors connected to the gate of a respective one of said second pair of transistors.
Claim 3
Dependent Claim
452 words
In an integrated circuit device formed on a semiconductor substrate, a Reset/Set latch comprising: a pair of voltage supply nodes; a first pair of insulated-gate field-effect transistors of one channel conductivity type, each transistor of said first pair of transistors including a source region and a drain region of the one conductivity type formed within the substrate, and including an insulated gate electrode on the substrate configured for inducing a conduction channel between said source region and said drain region of each of said first transistor pair, said source regions of said first transistor pair electrically connected to each other and to one of said pair of voltage supply nodes, said gate electrode of one transistor of said first transistor pair being electrically connected to said drain region of the other transistor of said first transistor pair, said gate electrode of said other of said first transistor pair being electrically connected to said drain region of said one of said first transistor pair, and said drain regions of said first transistor pair respectively defining first and second complementary data output nodes; a second pair of insulated-gate field-effect transistors of opposite channel conductivity type, each of said second pair of transistors including a source region and a drain region of the opposite conductivity type formed within the substrate, and including an insulated gate electrode on the substrate configured for inducing a conduction channel between said source region and said drain region of said second transistor pair, said gate electrodes of said second transistor pair respectively defining first and second data input nodes, said source regions of said second transistor pair electrically connected to each other and to the other of said pair of voltage supply nodes, and said drain regions of said second transistor pair respectively electrically connected to respective drain regions of said first transistor pair; each of said transistors of said second pair being formed within its own well region of the one conductivity type; a pair of ohmic contacts between said well regions and said other voltage supply node, each of said ohmic contacts including a heavily-doped contact region of the one conductivity type at a surface of the substrate and adjoining the repective well region; a pair of depletion-mode field-effect transistors of said opposite channel conductivity type, each having an implanted channel region of the opposite conductivity type formed in said semiconductor substrate, said source regions of said second transistor pair respectively serving as source regions of said depletion-mode transistors, said drain regions of said second transistor pair respectively serving as drain regions of said depletion-mode transistors, and the gate of each said depletion-mode transistors connected to the source of a respective one of said second pair of transistors.
Claim 4
Dependent Claim
452 words
In an integrated circuit device formed on a semiconductor substrate, a Reset/Set latch comprising: a pair of voltage supply nodes; a first pair of insulated-gate field-effect transistors of one channel conductivity type, each transistor of said first pair of transistors including a source region and a drain region of the one conductivity type formed within the substrate, and including an insulated gate electrode on the substrate configured for inducing a conduction channel between said source region and said drain region of each of said first transistor pair, said source regions of said first transistor pair electrically connected to each other and to one of said pair of voltage supply nodes, said gate electrode of one transistor of said first transistor pair being electrically connected to said drain region of the other transistor of said first transistor pair, said gate electrode of said other of said first transistor pair being electrically connected to said drain region of said one of said first transistor pair, and said drain regions of said first transistor pair respectively defining first and second complementary data output nodes; a second pair of insulated-gate field-effect transistors of opposite channel conductivity type, each of said second pair of transistors including a source region and a drain region of the opposite conductivity type formed within the substrate, and including an insulated gate electrode on the substrate configured for inducing a conduction channel between said source region and said drain region of said second transistor pair, said gate electrodes of said second transistor pair respectively defining first and second data input nodes, said source regions of said second transistor pair electrically connected to each other and to the other of said pair of voltage supply nodes, and said drain regions of said second transistor pair respectively electrically connected to respective drain regions of said first transistor pair; each of said transistors of said second pair being formed within its own well region of the one conductivity type; a pair of ohmic contacts between said well regions and said other voltage supply node, each of said ohmic contacts including a heavily-doped contact region of the one conductivity type at a surface of the substrate and adjoining the repective well region; a pair of depletion-mode field-effect transistors of said opposite channel conductivity type, each having an implanted channel region of the opposite conductivity type formed in said semiconductor substrate, said source regions of said second transistor pair respectively serving as source regions of said depletion-mode transistors, said drain regions of said second transistor pair respectively serving as drain regions of said depletion-mode transistors, and the gate of each said depletion-mode transistors connected to the source of a respective one of said second pair of transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-20 | 1988-05-21 | 1988-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-20 | 1992-05-21 | 1992-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-20 | 1996-05-21 | 1996-11-20 | $7700.00 | Window Closed / Lapsed |