Patent US4481481A successfully refreshed from Google Patents.
US4481481A
Expired / Lapsed
US
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Buffer inverter circuit with adaptive bias
Assignee: National Semiconductor Corp
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Filing: 1983-02-11
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Granted: 1984-11-06
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Expires: 2003-02-11
Abstract
Abstract An integrated circuit buffer inverter is created by cascading an emitter follower stage with a common emitter stage. Both stages include constant collector current loads. The emitter follower stage is adaptively biased from a current mirror that is driven from the collector of the emitter follower for the purpose of maximizing bipolar drive to the common emitter stage.
Inventors
- 👤 Robert S. Sleeth
- 👤 Dennis M. Monticelli
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 03:59
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/02; H03F1/0205; H03F1/0261; H03F1/30; H03F1/302
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
83 words
An inverting buffer amplifier circuit having input and output terminals, said circuit comprising a common emitter output stage driving said output terminal; an emitter follower input stage driven from said input terminal and driving the base of said output stage, said emitter follower including a means for sourcing current in series with its collector; and a current mirror having an input coupled to be driven from said collector of said emitter follower and an output coupled to said base of said output stage.
Claim 2
Dependent Claim
83 words
An inverting buffer amplifier circuit having input and output terminals, said circuit comprising a common emitter output stage driving said output terminal; an emitter follower input stage driven from said input terminal and driving the base of said output stage, said emitter follower including a means for sourcing current in series with its collector; and a current mirror having an input coupled to be driven from said collector of said emitter follower and an output coupled to said base of said output stage.
Claim 3
Dependent Claim
13 words
The circuit of claim 1 wherein said current mirror has unity current gain.
Claim 4
Dependent Claim
26 words
The circuit of claim 1 wherein said current mirror input is coupled to said collector of said emitter follower by means of a forward biased diode.
Claim 5
Dependent Claim
136 words
An inverting buffer amplifier circuit having input and output terminals, said circuit comprising: first and second supply rails connectable to a source of operating potential; first transistor means having an emitter coupled to said second supply rail, a collector coupled to said output terminal and a base; second transistor means having an emitter coupled to said base of said first transistor means, a base coupled to said input terminal and a collector; first constant current means couple between said first supply rail and said collector of said first transistor means; second constant current means coupled between and first supply rail and said collector of said second transistor means; and current mirror means having an input coupled to said collector of said second transistor means and an output coupled to said base of said first transistor means.
Claim 6
Dependent Claim
136 words
An inverting buffer amplifier circuit having input and output terminals, said circuit comprising: first and second supply rails connectable to a source of operating potential; first transistor means having an emitter coupled to said second supply rail, a collector coupled to said output terminal and a base; second transistor means having an emitter coupled to said base of said first transistor means, a base coupled to said input terminal and a collector; first constant current means couple between said first supply rail and said collector of said first transistor means; second constant current means coupled between and first supply rail and said collector of said second transistor means; and current mirror means having an input coupled to said collector of said second transistor means and an output coupled to said base of said first transistor means.
Claim 7
Dependent Claim
26 words
The circuit of claim 4 wherein said current mirror input is coupled to said collector of said second transistor means by first forward biased diode means.
Claim 8
Dependent Claim
26 words
The circuit of claim 5 wherein said first forward biased diode means is created from a fourth transistor means having a base returned to its collector.
Claim 9
Dependent Claim
53 words
The circuit of claim 4 wherein said current mirror means comprise: third transistor means having an emitter coupled to said first supply rail a collector that constitutes said current mirror output and a base; and second diode means, poled for forward conduction, coupled between said base and emitter of said third transistor means.
Claim 10
Dependent Claim
23 words
The circuit of claim 7 wherein said second diode means is created from fifth transistor means having a base returned to its collector.
References Cited (Backward Citations)
US4371792A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-06 | 1988-05-07 | 1988-11-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-06 | 1992-05-07 | 1992-11-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-06 | 1996-05-07 | 1996-11-06 | $7700.00 | Window Closed / Lapsed |