Patent US4479066A successfully refreshed from Google Patents.
US4479066A
Expired / Lapsed
US
⏱️ 0.0 years remaining
AC/DC Current divider circuit
Assignee: Nokia Bell Labs
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Filing: 1982-05-13
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Granted: 1984-10-23
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Expires: 2002-05-13
Abstract
Abstract There is disclosed a circuit, using integrated techniques, for dividing the AC component of an input signal by the DC component of that signal and then muitiplying the signal by a fixed DC current. This circuit is useful in opto-coupled gain control devices where the output AC signal must be gain adjusted for the light transfer characteristics of the opto-couplers.
Inventors
- 👤 Milton L. Embree
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:02
CPC Classifications
H; H04; H04M; H04M1/00; H04M1/003; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/3084
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
146 words
A circuit having an output terminal and an input terminal for accepting an input current having an AC component and a DC component, said circuit comprising means for separating said input current into first and second currents in a controlled proportion, each of said first and second currents having an AC component and a DC component, means responsive to said first current for establishing a control current substantially equal to said first current, said control current having an AC component and a DC component, a source of a DC reference current, said separating means including means responsive to said DC reference current and to said control current for controlling said proportion such that the DC component of said control current is substantially equal to said DC reference current, and means for supplying at said output terminal a signal representing the AC component of said control current.
Claim 2
Dependent Claim
146 words
A circuit having an output terminal and an input terminal for accepting an input current having an AC component and a DC component, said circuit comprising means for separating said input current into first and second currents in a controlled proportion, each of said first and second currents having an AC component and a DC component, means responsive to said first current for establishing a control current substantially equal to said first current, said control current having an AC component and a DC component, a source of a DC reference current, said separating means including means responsive to said DC reference current and to said control current for controlling said proportion such that the DC component of said control current is substantially equal to said DC reference current, and means for supplying at said output terminal a signal representing the AC component of said control current.
Claim 3
Dependent Claim
14 words
The invention set forth in claim 1 wherein said DC reference current is controllable.
Claim 4
Dependent Claim
70 words
The invention set forth in claim 1 wherein said separating means includes first and second transistors having a split ratio S of collector current of said first transistor to total collector current of said both transistors expressed as I 1 divided by I 1 plus I 2 , where I 1 is the collector current of said first transistor and I 2 is the collector current of said second transistor.
Claim 5
Dependent Claim
20 words
The invention set forth in claim 3 wherein said controlled proportion means includes the base current of said second transistor.
Claim 6
Dependent Claim
18 words
The invention set forth in claim 4 wherein said control current establishing means includes a current mirror circuit.
Claim 7
Dependent Claim
154 words
A circuit having an output terminal and an input terminal for accepting an input signal having an AC component and a DC component, said circuit comprising means for separating said input signal into first and second currents in a proportion controlled by a balancing current applied to a control input of said separating means, each of said first and second currents having an AC component and a DC component, a summing node connected to said output terminal, means responsive to said first current for establishing at said summing node a control current substantially equal to said first current, said control current having an AC component and a DC component, means for further establishing at said summing node a reference DC current, means for interconnecting said summing node and said control input to provide said balancing current, and means for providing at said output terminal a signal representing the AC component of said control current.
Claim 8
Dependent Claim
154 words
A circuit having an output terminal and an input terminal for accepting an input signal having an AC component and a DC component, said circuit comprising means for separating said input signal into first and second currents in a proportion controlled by a balancing current applied to a control input of said separating means, each of said first and second currents having an AC component and a DC component, a summing node connected to said output terminal, means responsive to said first current for establishing at said summing node a control current substantially equal to said first current, said control current having an AC component and a DC component, means for further establishing at said summing node a reference DC current, means for interconnecting said summing node and said control input to provide said balancing current, and means for providing at said output terminal a signal representing the AC component of said control current.
Claim 9
Dependent Claim
17 words
The invention set forth in claim 6 wherein said DC reference current is a controllable current source.
Claim 10
Dependent Claim
74 words
The invention set forth in claim 6 wherein said separating means includes first and second transistors having commonly connected emitter electrodes for establishing a split ratio of collector current of said first transistor to total collector current of both transistors expressed as I 1 divided by I 1 plus I 2 , where I 1 is said collector current of said first transistor and I 2 is the collector current of said second transistor.
Claim 11
Dependent Claim
19 words
The invention set forth in claim 7 wherein said balancing current is the base current of said second transistor.
Claim 12
Dependent Claim
18 words
The invention set forth in claim 9 wherein said control current establishing means includes a current mirror circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-23 | 1988-04-23 | 1988-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-23 | 1992-04-23 | 1992-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-23 | 1996-04-23 | 1996-10-23 | $7700.00 | Window Closed / Lapsed |