US4477886A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sense/restore circuit for dynamic random access memory
Assignee: National Semiconductor Corp
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Filing: 1982-02-26
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Granted: 1984-10-16
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Expires: 2002-02-26
Abstract
Abstract In a capacitive storage integrated circuit dynamic random access memory having a cross-coupled transistor sense amplifier coupled to a bit line wherein capacitive storage cells are coupled to the bit line through transistor transfer gates, means are provided for restoring charge on the capacitive storage cell by recharging the memory cells directly rather than through the bit lines. Specifically, each storage cell has one terminal coupled to one electrode terminal of the transistor transfer gate and its other terminal coupled to a switched voltage reference. The storage cell is not referenced to a fixed ground level.
Inventors
- 👤 Alexander C. Au
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:27
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4074
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
159 words
In an integrated circuit memory device wherein a capacitive storge memory cell having a first terminal and a second terminal is coupled at said first terminal through a transfer gate to a bit line, the improvement for recharging said memory cell, comprising: decoupling means coupled to said transfer gate for decoupling said first terminal from said bit line, said decoupling means including a word line voltage source for varying the magnitude of a charge on a word line connected to said transfer gate to thereby control the conduction of said transfer gate; and setting means coupled to said second terminal for setting a voltage level at said second terminal independently of said bit line alternatively to a first voltage level for recharging said memory cell during a restoration cycle, and to a second voltage level for reference during a read cycle, said memory cell being solely dependent for refreshing on said setting means voltage level during said restoration cycle.
Claim 2
Dependent Claim
159 words
In an integrated circuit memory device wherein a capacitive storge memory cell having a first terminal and a second terminal is coupled at said first terminal through a transfer gate to a bit line, the improvement for recharging said memory cell, comprising: decoupling means coupled to said transfer gate for decoupling said first terminal from said bit line, said decoupling means including a word line voltage source for varying the magnitude of a charge on a word line connected to said transfer gate to thereby control the conduction of said transfer gate; and setting means coupled to said second terminal for setting a voltage level at said second terminal independently of said bit line alternatively to a first voltage level for recharging said memory cell during a restoration cycle, and to a second voltage level for reference during a read cycle, said memory cell being solely dependent for refreshing on said setting means voltage level during said restoration cycle.
Claim 3
Dependent Claim
26 words
The memory device of claim 1, wherein a timer is connected to said memory device to provide a clock pulse to said word line voltage source.
Claim 4
Dependent Claim
40 words
In a memory device according to claim 1, the improvement wherein said voltage setting means is operative to provide a reference level for said memory cell at a voltage level other than ground level when said transfer gate is active.
Claim 5
Dependent Claim
49 words
In a memory device according to claim 3, the improvement wherein said voltage setting means is operative to set a voltage level at a level when said transfer gate is active which is sufficient to cause said transfer gate to become reverse biased when said transfer gate is deactivated.
References Cited (Backward Citations)
US3737879A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-16 | 1988-04-16 | 1988-10-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-16 | 1992-04-16 | 1992-10-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-16 | 1996-04-16 | 1996-10-16 | $7700.00 | Window Closed / Lapsed |