Abstract A dynamic type MOS memory device comprises a plurality of word lines, selecting switch MOSFETs which are disposed in correspondence with the respective word lines, a control circuit for controlling the selecting switch MOSFETs, MOSFETs which are disposed between the respective word lines and the ground potential and which are used as resistance means, and an inverter circuit which receives timing signals to be applied to input side electrodes of the selecting switch MOSFETs and which supplies the MOSFETs as the resistance means with control signals for bringing these MOSFETs into "off" states. The timing signal is brought into a supply voltage level substantially in synchronism with the completion of the operation of the control circuit. Accordingly, a dynamic type MOS memory device whose operating speed has been rendered high can be provided.
A dynamic type MOS memory device comprising: a plurality of gate lines and a plurality of selecting switch MOSFETs which are disposed in correspondence with the respective gate lines: a control circuit for controlling said plurality of selecting switch MOSFETs; a plurality of resistance means which are disposed between the respective gate lines and the ground potential and each of which has a control terminal; and an inverter circuit which receives timing signals to be applied to input side electrodes of the respective selecting switch MOSFETs and which delivers control signals to the control terminals; wherein said timing signals are brought into a supply voltage level substantially in synchronism with completion of an operation of said control circuit.
Claim 2
Dependent Claim
118 words
A dynamic type MOS memory device comprising: a plurality of gate lines and a plurality of selecting switch MOSFETs which are disposed in correspondence with the respective gate lines: a control circuit for controlling said plurality of selecting switch MOSFETs; a plurality of resistance means which are disposed between the respective gate lines and the ground potential and each of which has a control terminal; and an inverter circuit which receives timing signals to be applied to input side electrodes of the respective selecting switch MOSFETs and which delivers control signals to the control terminals; wherein said timing signals are brought into a supply voltage level substantially in synchronism with completion of an operation of said control circuit.
Claim 3
Dependent Claim
33 words
A dynamic type MOS memory device according to claim 1, wherein said gate lines are gate lines corresponding to word lines for selecting memory cells and data lines for selecting the memory cells.
Claim 4
Dependent Claim
50 words
A dynamic type MOS memory device according to claim 2, further comprising: a latch circuit which is disposed in correspondence with said each word line and which makes the non-selected word line a low impedance and makes the selected word line a high impedance by detecting a signal appearing thereon.