Dual threshold decoder for convolutional self-orthogonal codes

Claim 1

A decoder (10) for convolutional self-orthogonal codes comprising a multistage syndrome register (16) for storing a plurality of parity bits (S 47 -S 0 ); a first majority logic circuit (24) responsive to both a predetermined selection of parity bits from said plurality of parity bits and a plurality of received information bits (X 1 -X 7 ) for generating a plurality of information correction bits (C 1 -C 7 ) which correspond in a one-to-one relationship with said plurality of information bits, each information bit comprising a first value (1) when a first threshold level is surpassed and a second value (0) when said first threshold level is not surpassed, said first majority logic circuit producing as an output a plurality of corrected information bits (X 1 -X 7 ; and a second majority logic circuit (26) responsive to the predetermined selection of parity bits from the multistage syndrome register for generating a plurality of syndrome correction bits (S 1 -S 7 ), each syndrome correction bit comprising a first value (1) when a second threshold level is surpassed and a second value (0) when said second threshold level is not surpassed, said second majority logic circuit producing as an output a plurality of corrected syndrome bits (S') which are subsequently applied as inputs to said multistage syndrome register to replace said predetermined selection of syndrome bits.