VMOS-FET IMPATT diode pulse bias circuit

Claim 1

A bias circuit for delivering high voltage and current pulses of specified duty factors and pulse widths to an IMPATT diode to generate RF pulses, comprising: an input switch serving primarily as an inport buffer and to achieve a proper polarity of an input signal; voltage translation means coupled to said input switch for permitting voltage level translation of said input signal to a new ground reference without distorting said input signal; a driver circuit coupled to said voltage translation means to amplify said input signal; a pulse level control circuit coupled to said driver circuit to regulate the amount of bias voltage applied to said driver circuit and thereby regulate the magnitude of amplification of said driver circuit; voltage to current converter means coupled to said driver for passing a sufficient voltage and current pulse to said IMPATT diode; an IMPATT diode coupled to said voltage to current converter means to generate an RF pulse; and a protection circuit coupled between said voltage to current converter means and said input switch to monitor voltage levels across said converter means and shut off said input switch when said IMPATT diode shorts out.