US4472875A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing an integrated circuit device
Assignee: AT&T Teletype Corp
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Filing: 1983-06-27
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Granted: 1984-09-25
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Expires: 2003-06-27
Abstract
Abstract A method for manufacturing an integrated circuit thermal print head is illustrated including transistor 20 and a resistor doped region 22 formed on a first surface of a silicon circuit wafer 10. A contamination barrier in the form of a moat 26 filled with silicon nitride 30 is formed around the transistor 20. A support wafer 50 is secured to the first surface of the circuit wafer 10 by an adhesive layer 58. The circuit wafer 10 is thinned, and the exposed surface of the circuit wafer 10 is photoshaped to define wafer segments 68 positioned over the resistor doped region 22.
Inventors
- 👤 Raymond R. Christian
- 👤 Harry Sue
- 👤 Joseph C. Zuercher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:41
CPC Classifications
B; B41; B41J; B41J2/00; B41J2/315; B41J2/32; B41J2/35; B41J2/355; Y; Y10; Y10S; Y10S438/00; Y10S438/975
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
204 words
A method for manufacturing an integrated circuit device comprising the steps of: (A) processing a silicon circuit wafer (10) to form an integrated circuit (12) and at least one alignment pattern (34) on a first surface of the circuit wafer (10), said integrated circuit (12) includes an active circuit (20) and a passive heating element (22) controlled by said active circuit (20); (B) surrounding the active circuit (20) with a barrier (26, 30) to environmental contaminants; (C) preparing the surface of a support wafer (50) for subsequent processing; (D) positioning the first surface of the circuit wafer (10) opposing a first surface of the support wafer (50); (E) forming a layer of adhesive (58) on the opposing first surfaces of said circuit (10) and said support (50) wafers so as to cause the two wafers to adhere together forming a wafer sandwich (60); (F) photoshaping an opening (66) through the circuit wafer (10) to expose indicia (34a) corresponding to the alignment pattern (34); (G) photoshaping the circuit wafer (10) using the indicia (34a) exposed in Step F to produce an isolated circuit wafer section (68) disposed over said passive heating element (22); and (H) slicing the wafer sandwich (60) into integrated circuit chips (62).
Claim 2
Independent Claim
204 words
A method for manufacturing an integrated circuit device comprising the steps of: (A) processing a silicon circuit wafer (10) to form an integrated circuit (12) and at least one alignment pattern (34) on a first surface of the circuit wafer (10), said integrated circuit (12) includes an active circuit (20) and a passive heating element (22) controlled by said active circuit (20); (B) surrounding the active circuit (20) with a barrier (26, 30) to environmental contaminants; (C) preparing the surface of a support wafer (50) for subsequent processing; (D) positioning the first surface of the circuit wafer (10) opposing a first surface of the support wafer (50); (E) forming a layer of adhesive (58) on the opposing first surfaces of said circuit (10) and said support (50) wafers so as to cause the two wafers to adhere together forming a wafer sandwich (60); (F) photoshaping an opening (66) through the circuit wafer (10) to expose indicia (34a) corresponding to the alignment pattern (34); (G) photoshaping the circuit wafer (10) using the indicia (34a) exposed in Step F to produce an isolated circuit wafer section (68) disposed over said passive heating element (22); and (H) slicing the wafer sandwich (60) into integrated circuit chips (62).
Claim 3
Dependent Claim
29 words
The method of claim 1 which further includes the step of thinning the circuit wafer (10) prior to Step G to reduce the thickness of the wafer segments (68).
Claim 4
Dependent Claim
35 words
The method of claim 1 which further includes the step of placing a layerof material (36), which provides a barrier to environmental contaminants, over the surface of the circuit wafer (10) prior to Step E.
Claim 5
Dependent Claim
15 words
The method of claim 3 wherein the circuit wafer (10) has a <100> crystalline structure.
Claim 6
Dependent Claim
29 words
The method of claim 1 which further includes outgassing the adhesive (58) applied in Step E prior to adhesion of the wafers (10, 50) into a wafer sandwich (60).
Claim 7
Dependent Claim
23 words
The method of claim 1 wherein the barrier (26, 30) is in the form of a moat (26) filled with silicon nitride (30).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-09-25 | 1988-03-26 | 1988-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-25 | 1992-03-26 | 1992-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-25 | 1996-03-26 | 1996-09-25 | $7700.00 | Window Closed / Lapsed |