Method of and means for synchronizing a receiving section of a digital telecommunication system

Claim 3

The method defined in claim 1 wherein said incoming data words are transmitted with invariable first bits.

Claim 4

A circuit arrangement for timing the operation of a receiving section of a terminal of a digital telecommunication system in which the reception of incoming data words occurs during a predetermined fraction of a recurrent time slot, said data words being in the form of bipolar signals having rectangular envelopes of logical values, each of said logical values being defined by a respective code combination of voltage pulses of opposite polarities, comprising: a time base generating a succession of clock pulses for synchronizing said receiving section with the source of the incoming data words, said time base including a local oscillator provided with a phase-locking loop; coupling means connected to a signal link carrying said incoming data words; peak-detector means connected to said coupling means for ascertaining the arrival of a first bit of an incoming data word; and pulse-forming means connected to said peak-detector means for producing a series of control pulses each substantially conforming to said envelopes, each control pulse having a duration not exceeding said predetermined fraction of a time slot and further having a leading edge coinciding with the first bit of an incoming data word, said pulse-forming means having an output connected to a phase-stabilizing input of said phase-locking loop.

Claim 5

A circuit arrangement for timing the operation of a receiving section of a terminal of a digital telecommunication system in which the reception of incoming data words occurs during a predetermined fraction of a recurrent time slot, said data words being in the form of bipolar signals having rectangular envelopes of logical values, each of said logical values being defined by a respective code combination of voltage pulses of opposite polarities, comprising: a time base generating a succession of clock pulses for synchronizing said receiving section with the source of the incoming data words, said time base including a local oscillator provided with a phase-locking loop; coupling means connected to a signal link carrying said incoming data words; peak-detector means connected to said coupling means for ascertaining the arrival of a first bit of an incoming data word; and pulse-forming means connected to said peak-detector means for producing a series of control pulses each substantially conforming to said envelopes, each control pulse having a duration not exceeding said predetermined fraction of a time slot and further having a leading edge coinciding with the first bit of an incoming data word, said pulse-forming means having an output connected to a phase-stabilizing input of said phase-locking loop.

Claim 6

A circuit arrangement as defined in claim 3 wherein said first bit has an invariable configuration, said peak-detector means being biased to respond to a rising flank of the second voltage pulse of said first bit.

Claim 7

A circuit arrangement as defined in claim 4 wherein said pulse-forming means includes a voltage divider for deriving from the output of said peak-detector means a reference level of predetermined polarity lower than the peaks of the voltage pulses of the same polarity, and comparison means with inputs connected to said voltage divider and to said coupling means for emitting output pulses in response to signal voltages exceeding said reference level.

Claim 8

A circuit arrangement as defined in claim 5 wherein said pulse-forming means further comprises integrating means connected to said comparison means for receiving said output pulses.

Claim 9

A circuit arrangement as defined in claim 5 or 6 wherein said voltage divider establishes said reference level at half the amplitude of said peaks.

Claim 10

A circuit arrangement as defined in claim 3, 4, 5 or 6 wherein said pulse-forming means includes a monoflop having an off-normal period equaling half of said time slot.