Patent US4472773A successfully refreshed from Google Patents.
US4472773A
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Instruction decoding logic system
Assignee: Bull HN Information Systems Inc
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Filing: 1981-09-16
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Granted: 1984-09-18
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Expires: 2001-09-16
Abstract
Abstract A decoding logic system in a logic control system of a data processing system is disclosed, wherein the data processing system is comprized of a main memory unit communicating with the logic control system by way of a common communication bus, and wherein the logic control system and a CPU (central processing unit) communicate by way of a local communication bus. In response to a CPU request, CPU instructions stored in the main memory unit are received by the logic decoding system, and presented to the CPU in such a manner as to accommodate both memory bit and CPU computed bit modifications to the instructions during instruction execution, while avoiding interruptions in CPU activity caused by information transfer delays internal to the logic decoding system. Instruction modification also may be effected by incrementing or decrementing the instructions under firmware control.
Inventors
- 👤 Philip E. Stanley
- 👤 William E. Woods
- 👤 Richard A. Lemay
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 14:10
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30145; G06F9/30181
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
311 words
A decoding logic system in electrical communication with a central processing unit (CPU) having a firmware control system, and receiving binary coded information from a memory system, said decoding logic system which comprises: (a) first logic means for receiving first bit field signals of said binary coded information from said memory system during a first cycle of operation, said first logic means including register means responsive to a first plurality of control signals from said firmware control system for storing said first bit field signals received by input terminals during said first cycle of operation for transfer to said CPU by output terminals during a second cycle of operation, said first logic means including bidirectional information path means coupled between the input terminals and the output terminals of said register means for transferring said first bit field signals to said CPU during said first cycle of operation in response to said first plurality of control signals, and for reloading said first bit field signals in said register means in response to said first plurality of control signals during a second cycle of operation and subsequent cycles of operation for transfer to said CPU; (b) second logic means responsive to a second plurality of control signals from said firmware control system for storing second bit field signals of said binary coded information received from said memory system during said first cycle of operation for transfer to said CPU and responsive to said second plurality of control signals for storing computed value signals from said CPU during said second and said subsequent cycles of operation; wherein said first bit field signals and said second bit field signals are transferred to said CPU during said first cycle of operation, and said first bit field signals and said computed value signals are transferred to said CPU during said second and said subsequent cycles of operation.
Claim 2
Dependent Claim
311 words
A decoding logic system in electrical communication with a central processing unit (CPU) having a firmware control system, and receiving binary coded information from a memory system, said decoding logic system which comprises: (a) first logic means for receiving first bit field signals of said binary coded information from said memory system during a first cycle of operation, said first logic means including register means responsive to a first plurality of control signals from said firmware control system for storing said first bit field signals received by input terminals during said first cycle of operation for transfer to said CPU by output terminals during a second cycle of operation, said first logic means including bidirectional information path means coupled between the input terminals and the output terminals of said register means for transferring said first bit field signals to said CPU during said first cycle of operation in response to said first plurality of control signals, and for reloading said first bit field signals in said register means in response to said first plurality of control signals during a second cycle of operation and subsequent cycles of operation for transfer to said CPU; (b) second logic means responsive to a second plurality of control signals from said firmware control system for storing second bit field signals of said binary coded information received from said memory system during said first cycle of operation for transfer to said CPU and responsive to said second plurality of control signals for storing computed value signals from said CPU during said second and said subsequent cycles of operation; wherein said first bit field signals and said second bit field signals are transferred to said CPU during said first cycle of operation, and said first bit field signals and said computed value signals are transferred to said CPU during said second and said subsequent cycles of operation.
Claim 3
Dependent Claim
316 words
A decoding logic system in electrical communication with a central processing unit (CPU) having a firmware control system, and receiving binary coded information from a memory system, said decoding logic system which comprises: (a) first logic means for receiving first bit field signals of said binary coded information from said memory system during a first cycle of operation, said first logic means including register means responsive to a first plurality of control signals from said firmware control system for storing said first bit field signals received by input terminals during said first cycle of operation for transfer to said CPU by output terminals during a second cycle of operation, said first logic means including bidirectional information path means coupled between the input terminals and the output terminals of said register means for transferring said first bit field signals to said CPU during said first cycle of operation in response to said first plurality of control signals, and for reloading said first bit field signals in said register means in response to said first plurality of control signals during a second cycle of operation and subsequent cycles of operation for transfer to said CPU; (b) second logic means coupled to said CPU and responsive to a second plurality of control signals for storing computed value signals received from said CPU during said second and said subsequent cycles of operation; and (c) third logic means coupled to said memory system and said second logic means and responsive to said first plurality of control signals from said firmware control system for storing second bit field signals of said binary coded information during said first cycle of operation for transfer to said CPU, said third logic means being responsive to a third plurality of control signals from said firmware control system for storing said computed value signals during said second and subsequent cycles of operation for transfer to said CPU.
Claim 4
Dependent Claim
316 words
A decoding logic system in electrical communication with a central processing unit (CPU) having a firmware control system, and receiving binary coded information from a memory system, said decoding logic system which comprises: (a) first logic means for receiving first bit field signals of said binary coded information from said memory system during a first cycle of operation, said first logic means including register means responsive to a first plurality of control signals from said firmware control system for storing said first bit field signals received by input terminals during said first cycle of operation for transfer to said CPU by output terminals during a second cycle of operation, said first logic means including bidirectional information path means coupled between the input terminals and the output terminals of said register means for transferring said first bit field signals to said CPU during said first cycle of operation in response to said first plurality of control signals, and for reloading said first bit field signals in said register means in response to said first plurality of control signals during a second cycle of operation and subsequent cycles of operation for transfer to said CPU; (b) second logic means coupled to said CPU and responsive to a second plurality of control signals for storing computed value signals received from said CPU during said second and said subsequent cycles of operation; and (c) third logic means coupled to said memory system and said second logic means and responsive to said first plurality of control signals from said firmware control system for storing second bit field signals of said binary coded information during said first cycle of operation for transfer to said CPU, said third logic means being responsive to a third plurality of control signals from said firmware control system for storing said computed value signals during said second and subsequent cycles of operation for transfer to said CPU.
Claim 5
Dependent Claim
326 words
A decoding logic system in electrical communication with a central processing unit (CPU) having a firmware control system, and receiving binary coded CPU instructions from a memory system, said decoding logic system which comprises: (a) first logic means for receiving binary operation code signals of said binary coded CPU instructions from said memory system during a first cycle of operation, said first logic means including register means responsive to a first plurality of control signals from said firmware control system for storing said binary operation code signals received by input terminals during said first cycle of operation for transfer to said CPU by output terminals during a second cycle of operation, said first logic means including bidirectional information path means coupled between the input terminals and the output terminals of said register means for transferring said binary operation code signals to said CPU during said first cycle of operation in response to said first plurality of control signals from said firmware control system, and for reloading said binary operation code signals in said first register means in response to said first plurality of control signals during a second cycle of operation and subsequent cycles of operation for transfer to said CPU; (b) second logic means coupled to said CPU and responsive to a second plurality of control signals from said firmware control system for storing computed value signals received from said CPU during said second and said subsequent cycles of operation; and (c) third logic means coupled to said memory system and said second logic means and responsive to said first plurality of control signals from said firmware control system for storing said computed value signals of said binary coded CPU instructions during said first cycle of operation for transfer to said CPU, said third logic means being responsive to a third plurality of control signals from for storing said computed value signals during said second and subsequent cycles of operation for transfer to said CPU.
Claim 6
Dependent Claim
326 words
A decoding logic system in electrical communication with a central processing unit (CPU) having a firmware control system, and receiving binary coded CPU instructions from a memory system, said decoding logic system which comprises: (a) first logic means for receiving binary operation code signals of said binary coded CPU instructions from said memory system during a first cycle of operation, said first logic means including register means responsive to a first plurality of control signals from said firmware control system for storing said binary operation code signals received by input terminals during said first cycle of operation for transfer to said CPU by output terminals during a second cycle of operation, said first logic means including bidirectional information path means coupled between the input terminals and the output terminals of said register means for transferring said binary operation code signals to said CPU during said first cycle of operation in response to said first plurality of control signals from said firmware control system, and for reloading said binary operation code signals in said first register means in response to said first plurality of control signals during a second cycle of operation and subsequent cycles of operation for transfer to said CPU; (b) second logic means coupled to said CPU and responsive to a second plurality of control signals from said firmware control system for storing computed value signals received from said CPU during said second and said subsequent cycles of operation; and (c) third logic means coupled to said memory system and said second logic means and responsive to said first plurality of control signals from said firmware control system for storing said computed value signals of said binary coded CPU instructions during said first cycle of operation for transfer to said CPU, said third logic means being responsive to a third plurality of control signals from for storing said computed value signals during said second and subsequent cycles of operation for transfer to said CPU.
Claim 7
Dependent Claim
359 words
A decoding logic system in electrical communication with a central processing unit (CPU) having a firmware control system, and receiving binary coded CPU instructions from a memory system, said decoding logic system which comprises: (a) first logic means for receiving binary operation code signals of said binary coded CPU instructions from said memory system during a first cycle of operation, said first logic means including register means responsive to a first plurality of control signals from said firmware control system for storing said binary operation code signals received by input terminals during said first cycle of operation for transfer to said CPU by output terminals during a second cycle of operation, said first logic means including bidirectional information path means coupled between the input terminals and the output terminals of said register means for transferring said binary operation code signals to said CPU during said first cycle of operation in response to said first plurality of control signals from said firmware control system, and for reloading said binary operation code signals in said first register means in response to said first plurality of control signals during a second cycle of operation and subsequent cycles of operation for transfer to said CPU; (b) second logic means coupled to said CPU and responsive to a second plurality of control signals from said firmware control system for storing computed value signals received from said CPU during said second and said subsequent cycles of operation; and (c) third logic means coupled to said memory system and said second logic means and responsive to said first plurality of control signals from said firmware control system for storing said computed value signals of said binary coded CPU instructions during said first cycle of operation for transfer to said CPU, said third logic means being responsive to a third plurality of control signals from said firmware control system for storing said computed value signals and said third logic means being responsive to a fourth plurality of control signals from said firmware control system for incrementing or decrementing the binary value of said stored value signals stored in said third logic means for transfer to said CPU.
Claim 8
Dependent Claim
359 words
A decoding logic system in electrical communication with a central processing unit (CPU) having a firmware control system, and receiving binary coded CPU instructions from a memory system, said decoding logic system which comprises: (a) first logic means for receiving binary operation code signals of said binary coded CPU instructions from said memory system during a first cycle of operation, said first logic means including register means responsive to a first plurality of control signals from said firmware control system for storing said binary operation code signals received by input terminals during said first cycle of operation for transfer to said CPU by output terminals during a second cycle of operation, said first logic means including bidirectional information path means coupled between the input terminals and the output terminals of said register means for transferring said binary operation code signals to said CPU during said first cycle of operation in response to said first plurality of control signals from said firmware control system, and for reloading said binary operation code signals in said first register means in response to said first plurality of control signals during a second cycle of operation and subsequent cycles of operation for transfer to said CPU; (b) second logic means coupled to said CPU and responsive to a second plurality of control signals from said firmware control system for storing computed value signals received from said CPU during said second and said subsequent cycles of operation; and (c) third logic means coupled to said memory system and said second logic means and responsive to said first plurality of control signals from said firmware control system for storing said computed value signals of said binary coded CPU instructions during said first cycle of operation for transfer to said CPU, said third logic means being responsive to a third plurality of control signals from said firmware control system for storing said computed value signals and said third logic means being responsive to a fourth plurality of control signals from said firmware control system for incrementing or decrementing the binary value of said stored value signals stored in said third logic means for transfer to said CPU.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-09-18 | 1988-03-19 | 1988-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-18 | 1992-03-19 | 1992-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-18 | 1996-03-19 | 1996-09-18 | $7700.00 | Window Closed / Lapsed |