US4472645A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock circuit for generating non-overlapping pulses
Assignee: British Telecommunications PLC
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Filing: 1981-12-22
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Granted: 1984-09-18
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Expires: 2001-12-22
Abstract
Abstract A clock generator for producing a two phase output comprises a bistable circuit having two stages. The output of each stage is cross coupled to the input of the other and each cross coupling path includes a high-resistance transfer gate. Each transfer gate forms part of an RC delay element which is so arranged that at a transition of clock signals the output of one of the stages completes its transition substantially at the same time as the output of the other stage begins its transition. This results in non-overlapping outputs from the generator.
Inventors
- 👤 Lincoln D. White
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 04:17
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/151; H03K5/1515
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
154 words
A clock generator having a two phase output comprising a bistable circuit having two stages in which the output of each stage is cross coupled to one input of the other stage, said one input having an input capacitance associated therewith, each stage having a second input one of which is coupled to receive a clock signal, the other of which is coupled to receive the inverse of the clock signal, characterised in that each of the two stages is formed employing insulating gate field effect transistors and the cross coupling path to said one input of each stage includes a respective series resistance element forming with the input capacitance of that stage an RC delay element which is so coupled that at a transition of said clock signals the output of one of said stages completes its transition substantially at the same time as the output of the other stage begins its transition.
Claim 2
Dependent Claim
154 words
A clock generator having a two phase output comprising a bistable circuit having two stages in which the output of each stage is cross coupled to one input of the other stage, said one input having an input capacitance associated therewith, each stage having a second input one of which is coupled to receive a clock signal, the other of which is coupled to receive the inverse of the clock signal, characterised in that each of the two stages is formed employing insulating gate field effect transistors and the cross coupling path to said one input of each stage includes a respective series resistance element forming with the input capacitance of that stage an RC delay element which is so coupled that at a transition of said clock signals the output of one of said stages completes its transition substantially at the same time as the output of the other stage begins its transition.
Claim 3
Dependent Claim
36 words
A clock generator as claimed in claim 1 characterised in that the RC elements are coupled to produce a characteristic RC delay on alternate clock transitions, only one RC element being effective at any given transition.
Claim 4
Dependent Claim
21 words
A clock generator as claimed in claim 2 characterised in that each stage of the bistable circuit comprises a NOR gate.
Claim 5
Dependent Claim
63 words
A clock generator as claimed in claim 3 characterised in that each NOR gate comprises a pair of MOS transistors with respective sources and drains connected in parallel and with respective gate electrodes serving as a pair of inputs to the NOR gate with a common load transistor connected in series with said parallel connected sources and drains of the pair of transistors.
Claim 6
Dependent Claim
40 words
A clock generator as claimed in claim 4 characterised in that each series resistance element comprises a high resistance transfer MOS transistor having a gate electrode connected to a predetermined voltage and providing a predetermined resistance across its source-drain electrodes.
Claim 7
Dependent Claim
38 words
A clock generator as claimed in claim 4 or claim 5 characterised in that one of said load transistors is coupled to be driven by the clock signal and the other by the inverse of the clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-09-18 | 1988-03-19 | 1988-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-18 | 1992-03-19 | 1992-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-18 | 1996-03-19 | 1996-09-18 | $7700.00 | Window Closed / Lapsed |