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Patent US4471240A successfully refreshed from Google Patents.
US4471240A
Expired / Lapsed
US
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Power-saving decoder for memories
Assignee: Motorola Solutions Inc
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Filing: 1982-08-19
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Granted: 1984-09-11
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Expires: 2002-08-19
Abstract
Abstract A decoder for memories improves speed and reduces power consumption by gating the power to a parallel decoder to provide a signal to a bootstrap circuit for providing an enable signal at essentially the voltage present at a positive power supply terminal.
Inventors
- 👤 David Novosel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:22
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01714; H03K19/0008; H03K19/0016
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
211 words
A decoder for memories for providing an enable signal in response to an address signal, comprising: selection means coupled between a select node and a first power supply terminal for coupling the select node to the first power supply terminal when deselected by an address signal and for providing an open circuit therebetween when selected by the address signal; a first transistor having a first current electrode coupled to a second power supply terminal, a second current electrode coupled to the select node, and control electrode for receiving a select signal; an inverter having an input coupled to the select node, and an output; a second transistor having a first current electrode coupled to the select node, a control electrode coupled to the output of the inverter, and a second current electrode; a third transistor having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to the select node, and a control electrode coupled to the second current electrode of the second transistor; and bootstrap means having an input coupled to the second current electrode of the second transistor for coupling the second power supply terminal to the output node with a negligible voltage drop therebetween in response to the section means being selected.
Claim 2
Dependent Claim
211 words
A decoder for memories for providing an enable signal in response to an address signal, comprising: selection means coupled between a select node and a first power supply terminal for coupling the select node to the first power supply terminal when deselected by an address signal and for providing an open circuit therebetween when selected by the address signal; a first transistor having a first current electrode coupled to a second power supply terminal, a second current electrode coupled to the select node, and control electrode for receiving a select signal; an inverter having an input coupled to the select node, and an output; a second transistor having a first current electrode coupled to the select node, a control electrode coupled to the output of the inverter, and a second current electrode; a third transistor having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to the select node, and a control electrode coupled to the second current electrode of the second transistor; and bootstrap means having an input coupled to the second current electrode of the second transistor for coupling the second power supply terminal to the output node with a negligible voltage drop therebetween in response to the section means being selected.
Claim 3
Dependent Claim
139 words
The decoder of claim 1 wherein the bootstrap means comprises: a fourth transistor having a first current electrode coupled to the second power supply terminal, a control electrode coupled to the second current electrode of the second transistor, and a second current electrode for providing the enable signal; a fifth transistor having a first current electrode and a control electrode coupled to the control electrode of the fourth transistor, and a second current electrode; a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, and a second current electrode and a control electrode coupled to the second power supply terminal; and a capacitor having a first terminal coupled to the second current electrode of the fourth transistor, and a second terminal coupled to the second current electrode of the fifth transistor.
Claim 4
Dependent Claim
47 words
The decoder of claim 2 further comprising a seventh transistor having a control electrode coupled to the output of the inverter, a first current electrode coupled to the second current electrode of the fourth transistor, and a second current electrode coupled to the first power supply terminal.
Claim 5
Dependent Claim
155 words
A row decoder for memories for providing an enable signal to a word line in response to an address signal, comprising: selection means coupled between a select node and a first power supply terminal for coupling the select node to the first power supply terminal when deselected by an address signal and for providing an open circuit therebetween when selected by the address signal; coupling means for coupling a second power supply terminal to the select node when the selection means is selected in response to receiving a select signal, wherein said select signal is generated in response to a change in the address signal; and output means for providing the enable signal in response to the coupling means coupling the second power supply terminal to the select node, and holding the enable signal at essentially the voltage present at the second power supply terminal after removal of the select signal from the coupling means.
Claim 6
Dependent Claim
155 words
A row decoder for memories for providing an enable signal to a word line in response to an address signal, comprising: selection means coupled between a select node and a first power supply terminal for coupling the select node to the first power supply terminal when deselected by an address signal and for providing an open circuit therebetween when selected by the address signal; coupling means for coupling a second power supply terminal to the select node when the selection means is selected in response to receiving a select signal, wherein said select signal is generated in response to a change in the address signal; and output means for providing the enable signal in response to the coupling means coupling the second power supply terminal to the select node, and holding the enable signal at essentially the voltage present at the second power supply terminal after removal of the select signal from the coupling means.
Claim 7
Dependent Claim
44 words
The row decoder of claim 4, wherein the coupling means is an enhancement transistor having a first current electrode coupled to the second power supply terminal, a control electrode for receiving the select signal, and a second current electrode coupled to the select node.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-09-11 | 1988-03-12 | 1988-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-11 | 1992-03-12 | 1992-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-11 | 1996-03-12 | 1996-09-11 | $7700.00 | Window Closed / Lapsed |