US4470059A
Expired / Lapsed
US
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Gallium arsenide static induction transistor
Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
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Filing: 1982-04-19
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Granted: 1984-09-04
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Expires: 2002-04-19
Abstract
Abstract A gallium arsenide static induction transistor of normally-off type simple in manufacture and exhibiting a superior function and suitable for use in low and medium power operation in integrated circuit is obtained by arranging so that its channel region has a length l (μm), a width (μm) and an impurity concentration N (cm -3 ), and that the ratio l/w is 0.5-5.0 and that the product Nw 2 is not larger than 2.5×10 15 cm -3 .μm 2 .
Inventors
- 👤 Jun-ichi Nishizawa
- 👤 Tadahiro Ohmi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:52
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D62/116; H10D12/00; H10D30/00; H10D30/202; H10D62/17; H10D62/343; H10D62/80; H10D62/85
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
261 words
A gallium arsenide normally off static induction transistor formed in a chip having a first and a second main surface and responsive to a forward gate bias, comprising: an n type high resistivity gallium arsenide region having a donor concentration N D and disposed adjacent to said first main surface; a first n type low resistivity gallium arsenide region formed in said high resistivity gallium arsenide region adjacent to said first main surface; a second n type low resistivity gallium arsenide region formed adjacent to said high resistivity gallium arsenide region on the side opposite to said first main surface; and a p type low resistivity gallium arsenide gate region formed in said high resistivity gallium arsenide region adjacent to said first main surface, and substantially surrounding said first n type low resistivity gallium arsenide region, and extending toward said second main surface farther than said first n type low resistivity gallium arsenide region, and defining a channel region of a length l and a width w in said high resistivity gallium arsenide region said width w being less than the diffusion length of minority carriers in said high resistivity gallium arsenide region, the product of said donor concentration N D and the square of said width w, i.e. N D w 2 , being not greater than about 2.5×10 7 cm -1 , the ratio of said length l to said width w, i.e. l/w, being not smaller than about 1.0 and not greater than about 2.0, thereby establishing a potential barrier in said channel region at zero gate bias.
Claim 2
Dependent Claim
261 words
A gallium arsenide normally off static induction transistor formed in a chip having a first and a second main surface and responsive to a forward gate bias, comprising: an n type high resistivity gallium arsenide region having a donor concentration N D and disposed adjacent to said first main surface; a first n type low resistivity gallium arsenide region formed in said high resistivity gallium arsenide region adjacent to said first main surface; a second n type low resistivity gallium arsenide region formed adjacent to said high resistivity gallium arsenide region on the side opposite to said first main surface; and a p type low resistivity gallium arsenide gate region formed in said high resistivity gallium arsenide region adjacent to said first main surface, and substantially surrounding said first n type low resistivity gallium arsenide region, and extending toward said second main surface farther than said first n type low resistivity gallium arsenide region, and defining a channel region of a length l and a width w in said high resistivity gallium arsenide region said width w being less than the diffusion length of minority carriers in said high resistivity gallium arsenide region, the product of said donor concentration N D and the square of said width w, i.e. N D w 2 , being not greater than about 2.5×10 7 cm -1 , the ratio of said length l to said width w, i.e. l/w, being not smaller than about 1.0 and not greater than about 2.0, thereby establishing a potential barrier in said channel region at zero gate bias.
Claim 3
Dependent Claim
19 words
A gallium arsenide static induction transistor according to claim 1, wherein: said ratio l/w is at least about 1.
Claim 4
Dependent Claim
32 words
A gallium arsenide static induction transistor according to claim 1 or 2, wherein: said p type gate region extends from said first main surface divergently into said high resistivity gallium arsenide region.
Claim 5
Dependent Claim
40 words
A gallium arsenide static induction transistor according to claim 1 or 2, wherein: said p type gate region locally has a portion bulging in said high resistivity gallium arsenide region at a site located distant from said first main surface.
Claim 6
Dependent Claim
45 words
A gallium arsenide static induction transistor according to claim 1 or 2, wherein: said p type gate region extends to and contacts said second low resistivity gallium arsenide region, and thereby said channel region is disposed adjacent to said second low resistivity gallium arsenide region.
Claim 7
Dependent Claim
45 words
A gallium arsenide static induction transistor according to claim 1 or 2, wherein: said high resistivity gallium arsenide region includes a portion disposed between said channel region and said second low resistivity gallium arsenide region, said portion having a thickness not less than about l/2.
Claim 8
Dependent Claim
40 words
A gallium arsenide static induction transistor according to claim 6, further comprising: an insulating or semi-insulating region disposed between said high resistivity region portion and that surface of said p type gallium arsenide gate region not facing said channel region.
Claim 9
Dependent Claim
37 words
A gallium arsenide static induction transistor according to claim 7, wherein: said insulating region is made of a substance selected from the group of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, gallium oxynitride and their mixtures.
Claim 10
Dependent Claim
32 words
A gallium arsenide static induction transistor according to claim 1 or 2, wherein: said p type gate region extends from said first main surface divergently into said high resistivity gallium arsenide region.
Claim 11
Dependent Claim
40 words
A gallium arsenide static induction transistor according to claim 1 or 2, wherein: said p type gate region locally has a portion bulging in said high resistivity gallium arsenide region at a site located distant from said first main surface.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-09-04 | 1988-03-05 | 1988-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-04 | 1992-03-05 | 1992-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-04 | 1996-03-05 | 1996-09-04 | $7700.00 | Window Closed / Lapsed |