US4468789A
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US
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Method for serial transmission and receipt of binary information
Assignee: National Security Agency
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Filing: 1981-11-16
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Granted: 1984-08-28
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Expires: 2001-11-16
Abstract
Abstract An improved method for serial transmission of binary data. Data words are conveyed over a communications path by means of four discrete signals. Bit value detection circuitry within the transmitter sequentially tests the untransmitted bits. Upon detection of only a single value in all of the untransmitted bits, the value being all ZEROs or all ONEs depending on the embodiment, an end of word signal is transmitted. In the receiver, a register is initialized to the predetermined single value state. Upon receipt of a signal representing the alternate state, the corresponding bit in the register is changed. Receipt of the end of word signal stops the process, at which time the register contains the word which was to be transmitted, thus accelerating the speed at which certain words may be transmitted.
Inventors
- 👤 William E. Gromen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:42
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/0078; H04L1/0083; H04L7/00; H04L7/04
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
140 words
A method of transmission of a sequence of binary words, each word consisting of a plurality of bits, each bit having either a first value or a second value, comprising the steps of: (a) inserting a word into a word register; (b) detecting the value of each bit of said word in said register sequentially, beginning with an end-most bit; (c) transmitting, after each detection, a signal representative of the value of the detected bit; (d) testing, after each detection, all but the previously detected bits of the word in said register until no tested bits have the second value; (e) upon the occurance of no tested bits having the second value, transmitting a signal indicative of the end of transmission of the word; and (f) repeating steps (a) through (e) until all words in the sequence have been transmitted.
Claim 2
Independent Claim
140 words
A method of transmission of a sequence of binary words, each word consisting of a plurality of bits, each bit having either a first value or a second value, comprising the steps of: (a) inserting a word into a word register; (b) detecting the value of each bit of said word in said register sequentially, beginning with an end-most bit; (c) transmitting, after each detection, a signal representative of the value of the detected bit; (d) testing, after each detection, all but the previously detected bits of the word in said register until no tested bits have the second value; (e) upon the occurance of no tested bits having the second value, transmitting a signal indicative of the end of transmission of the word; and (f) repeating steps (a) through (e) until all words in the sequence have been transmitted.
Claim 3
Dependent Claim
19 words
The method of claim 1, further comprising the step of transmitting a bit delimiter signal between each bit signal.
Claim 4
Dependent Claim
47 words
The method of claim 1, wherein step (b) includes the further step of shifting all of said bits one stage in the direction of the detected bit and inserting a bit having said first value in the end-most stage opposite that previously occupied by the detected bit.
Claim 5
Dependent Claim
111 words
A method of reception of a sequence of binary words transmitted by the process of claim 1, comprising the steps of: (a) initializing each stage of a word composer register to said first value; (b) detecting each said transmitted signal sequentially; (c) upon detection of a signal representing said second value, inserting said second value into a stage of said word composer register, said stage corresponding to the original location of the bit represented by said detected signal in said word register; (d) detecting a signal indicative of the end of transmission of the word, and (e) repeating steps (a) through (d) until all words in the sequence have been received.
Claim 6
Dependent Claim
19 words
The method of claim 4, further comprising the step of detecting a bit delimiter signal between each bit signal.
Claim 7
Dependent Claim
17 words
The method of claim 5 wherein step (b) further includes asynchronously detecting each said transmitted signal sequentially.
Claim 8
Independent Claim
159 words
A method of transmission of a sequence of binary words of variable length, each word consisting of a plurality of bits, each bit having either a first value or a second value, comprising the steps of: (a) inserting a word into a word register, said word having any length up to and including the number of stages in said register; (b) detecting the value of each bit of said word in said register sequentially, beginning with an end-most bit; (c) transmitting, after each detection, a signal representative of the value of the detected bit; (d) testing, after each detection, all but the previously detected bits of the word in said register until no tested bits have the second value; (e) upon the occurance of no tested bits having the second value, transmitting a signal indicative of the end of transmission of the word; and (f) repeating steps (a) through (e) until all words in the sequence have been transmitted.
Claim 9
Independent Claim
159 words
A method of transmission of a sequence of binary words of variable length, each word consisting of a plurality of bits, each bit having either a first value or a second value, comprising the steps of: (a) inserting a word into a word register, said word having any length up to and including the number of stages in said register; (b) detecting the value of each bit of said word in said register sequentially, beginning with an end-most bit; (c) transmitting, after each detection, a signal representative of the value of the detected bit; (d) testing, after each detection, all but the previously detected bits of the word in said register until no tested bits have the second value; (e) upon the occurance of no tested bits having the second value, transmitting a signal indicative of the end of transmission of the word; and (f) repeating steps (a) through (e) until all words in the sequence have been transmitted.
Claim 10
Independent Claim
185 words
A method of transmission of a sequence of binary words, each word consisting of a plurality bits, wherein said sequence is a serial stream composed of four discrete types of signals including a first signal representing a first binary value, a second signal representing a second binary value, a third signal representing a bit delimiter and a fourth signal representing a word delimiter, comprising the steps of: (a) inserting a word into a word register; (b) transmitting said fourth signal; (c) detecting the value of each bit of said word in said register sequentially, beginning with an end-most bit; (d) transmitting, after each detection, said first or second signal, as appropriate, representative of the value of the detected bit; (e) testing, after each detection, all but the previously detected bits of the word in said register until no tested bits have the second value; (f) transmitting, after each test, said third signal; p1 (g) upon the occurance of no tested bits having the second value, transmitting said fourth signal; and (h) repeating steps (a) through (g) until all words in the sequence have been transmitted.
Claim 11
Independent Claim
185 words
A method of transmission of a sequence of binary words, each word consisting of a plurality bits, wherein said sequence is a serial stream composed of four discrete types of signals including a first signal representing a first binary value, a second signal representing a second binary value, a third signal representing a bit delimiter and a fourth signal representing a word delimiter, comprising the steps of: (a) inserting a word into a word register; (b) transmitting said fourth signal; (c) detecting the value of each bit of said word in said register sequentially, beginning with an end-most bit; (d) transmitting, after each detection, said first or second signal, as appropriate, representative of the value of the detected bit; (e) testing, after each detection, all but the previously detected bits of the word in said register until no tested bits have the second value; (f) transmitting, after each test, said third signal; p1 (g) upon the occurance of no tested bits having the second value, transmitting said fourth signal; and (h) repeating steps (a) through (g) until all words in the sequence have been transmitted.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-08-28 | 1988-02-27 | 1988-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-08-28 | 1992-02-27 | 1992-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-08-28 | 1996-02-27 | 1996-08-28 | $7700.00 | Window Closed / Lapsed |