Dual gate CMOS transistor circuits having reduced electrode capacitance

Claim 2

In combination: a plurality of P-channel transistors, each including a source, a drain, a source-adjacent gate, and a drain-adjacent gate, a plurality of N-channel transistors, each including a source, a drain, a source-adjacent gate, and a drain-adjacent gate, a plurality of input terminals, an output terminal, each source of said P-channel transistors being connected to a first reference potential, each drain of said P-channel transistors being connected to said output terminal, each source-adjacent gate of said P-channel transistors being connected to a respective input terminal, each drain-adjacent gate of said P-channel transistors being connected to a third reference potential sufficiently negative with respect to said first reference potential to exceed the turn-on potential thereof, the source-to-drain conduction paths of said N-channel transistors being connected in series in the order named between a second reference potential and said output terminal, said second reference potential being negative with respect to said first reference potential, each of the source-adjacent gates of said N-channel transistors being connected to a respective input terminal, each of the drain-adjacent gates of said N-channel transistors being connected to a fourth reference potential sufficiently positive with respect to said second reference potential to exceed the turn-on potential thereof.

Claim 3

In combination: a plurality of P-channel transistors, each including a source, a drain, a source-adjacent gate, and a drain-adjacent gate, a plurality of N-channel transistors, each including a source, a drain, a source-adjacent gate and a drain-adjacent gate, a plurality of input terminals, an output terminal, the source-to-drain conduction paths of said P-channel transistors being connected in series in the order named between a first reference potential and said output terminal, each of the source-adjacent gates of said P-channel transistors being connected to a respective input terminal, each of the drain-adjacent gates of said P-channel transistors connected to a third reference potential sufficiently negative with respect to said first reference potential to exceed the turn-on potential thereof, each source of said N-channel transistors being connected to a second reference potential, said second reference potential being negative with respect to said first reference potential, each of the drains of said N-channel transistors being connected to said output terminal, each of the source-adjacent gates of said N-channel transistors being connected to a respective input terminal, each of the drain-adjacent gates of said N-channel transistors being connected to a fourth reference potential sufficiently positive with respect to said second reference potential to exceed the turn-on potential thereof.

Claim 4

In combination: a plurality of P-channel transistors, each including a source, a drain, a source-adjacent gate, and a drain-adjacent gate, a plurality of N-channel transistors, each including a source, a drain, a source-adjacent gate and a drain-adjacent gate, a plurality of input terminals, an output terminal, the source-to-drain conduction paths of said P-channel transistors being connected in series in the order named between a first reference potential and said output terminal, each of the source-adjacent gates of said P-channel transistors being connected to a respective input terminal, each of the drain-adjacent gates of said P-channel transistors connected to a third reference potential sufficiently negative with respect to said first reference potential to exceed the turn-on potential thereof, each source of said N-channel transistors being connected to a second reference potential, said second reference potential being negative with respect to said first reference potential, each of the drains of said N-channel transistors being connected to said output terminal, each of the source-adjacent gates of said N-channel transistors being connected to a respective input terminal, each of the drain-adjacent gates of said N-channel transistors being connected to a fourth reference potential sufficiently positive with respect to said second reference potential to exceed the turn-on potential thereof.