Quad-gate demodulator circuit for capacitive transducers

Claim 2

A quad-gate demodulator circuit for use with a capacitive transducer of the type having a reference capacitor (C r ) and a primary capacitor (C p ) which vary differently in response to a quantity being measured wherein the improvement comprises: an alternating excitation voltage source (18); first and second analog gate means (G1,G4) interconnecting the source with the reference and primary capacitors to charge the capacitors during one polarity of the excitation voltage; third and fourth analog gate means (G2,G3) interconnecting the source with the reference and primary capacitors to discharge the capacitors during the other polarity of the excitation voltage; control signal generator means (78) connected to said analog gate means for rendering the first and second gate means simultaneously conducting for a first time period which is synchronized with said one excitation voltage polarity and for rendering the third and fourth gate means conducting for a second time period which is synchronized with the other excitation voltage polarity; and output means (24) connected to said gate means for developing an output voltage related to the capacitance differential of the reference and primary capacitors.

Claim 3

Apparatus as defined in claim 1 wherein the first and second time periods are equal to each other and are shorter in duration than the half-cycles of the excitation voltage.

Claim 4

Apparatus as defined in claim 1, wherein the alternating excitation voltage is a squarewave.

Claim 5

Apparatus as defined in claim 1, wherein the gate means comprise C-MOS gates.

Claim 6

Apparatus as defined in claim 1, further including coupling capacitor means (20,22) connected between the excitation voltage source and said gate means.

Claim 7

Apparatus as defined in claim 1, further including a capacitive transducer (12) having at least one element (40) which varies in physical aspect in response to a measured quantity, at least a portion of the primary capacitor being physically associated with said element so as to vary in capacitance along with the physical aspect.

Claim 8

A demodulator circuit for use with a capacitive transducer of the type having a reference capaacitor C r and primary capacitor C p which vary differently in response to changes in measured quantity where the improvement comprises: a first circuit leg (23) comprising the series combination of first and second analog gates G1 and G2; a second circuit leg (25) comprising the series combination of third and fourth analog gates G3 and G4; the first and second legs being connected in parallel wlith one another; an alternating excitation voltage source (18) connected commonly to the opposite ends of the legs (23,25) and generating a voltage having a peak-to-peak voltage value V p ; output filter means (24) connected in parallel with both of said legs; the reference capacitor C r being connected to the junction between the gates of the first leg (23) to charge through G1 and discharge through G2; the primary capacitor C p being connected to the junction between the gates of the second leg (25) to charge through G4 and discharge through G3; and means synchronized with the excitation voltage to render G1 and G4 simultaneously conducting for a first time period corresponding to a portion of one excitation voltage polarity and to render G2 and G3 simultaneously conducting for a second time period corresponding to a portion of the other excitation voltage polarity; whereby the voltage V o across the output filter means follows the relationship V.sub.o =V.sub.p (C.sub.p -C.sub.r)/(C.sub.p +C.sub.r).

Claim 9

A demodulator circuit for use with a capacitive transducer of the type having a reference capaacitor C r and primary capacitor C p which vary differently in response to changes in measured quantity where the improvement comprises: a first circuit leg (23) comprising the series combination of first and second analog gates G1 and G2; a second circuit leg (25) comprising the series combination of third and fourth analog gates G3 and G4; the first and second legs being connected in parallel wlith one another; an alternating excitation voltage source (18) connected commonly to the opposite ends of the legs (23,25) and generating a voltage having a peak-to-peak voltage value V p ; output filter means (24) connected in parallel with both of said legs; the reference capacitor C r being connected to the junction between the gates of the first leg (23) to charge through G1 and discharge through G2; the primary capacitor C p being connected to the junction between the gates of the second leg (25) to charge through G4 and discharge through G3; and means synchronized with the excitation voltage to render G1 and G4 simultaneously conducting for a first time period corresponding to a portion of one excitation voltage polarity and to render G2 and G3 simultaneously conducting for a second time period corresponding to a portion of the other excitation voltage polarity; whereby the voltage V o across the output filter means follows the relationship V.sub.o =V.sub.p (C.sub.p -C.sub.r)/(C.sub.p +C.sub.r).

Claim 10

Apparatus as defined in claim 7, wherein the excitation voltage is substantially a squarewave.

Claim 11

Apparatus as defined in claim 7, wherein said gates are C-MOS gates.

Claim 12

Apparatus as defined in claim 7, wherein said excitation voltage source and said means synchronized therewith for rendering the gates conducting are derived from a common logic circuit having an oscillator and logic means for frequency dividing and phase shifting voltage waveforms derived from the oscillator.

Claim 13

Apparatus as defined in claim 7, further comprising a quartz capsule transducer containing the reference and primary capacitors to produce changes in said capacitors in response to a measured quantity such as a fluid pressure.

Claim 14

Apparatus as defined in claim 7, wherein the conducting time periods are equal in length and occur substantially during the center portions of the excitation voltage half-cycles.