US4466110A
Expired / Lapsed
US
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Artificial sync signal adding circuit
Assignee: Faurecia Clarion Electronics Co Ltd
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Filing: 1981-12-07
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Granted: 1984-08-14
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Expires: 2001-12-07
Abstract
Abstract An artificial synchronizing signal adding circuit which comprises a discriminating circuit for discriminating a continuous synchronizing signal having a constant period among an information signal including the synchronizing signal and an artificial sync signal adding circuit for adding an artificial sync signal to a part of the information signal where the synchronizing signal is lacking in response to the discrimination of the discriminating circuit when the synchronizing signal is lacking.
Inventors
- 👤 Yoshio Kizaki
- 👤 Mitsugu Ikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:57
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0079; H04L7/0083
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
173 words
A synchronizing signal reconstituting circuit which comprises: a receiving means for receiving an input signal including an information signal and a synchronizing signal having a constant period; a synchronizing signal discriminating means for discriminating said synchronizing signal in said input signal from said receiving means; an artificial synchronizing signal generating means for generating an artificial synchronizing signal when a synchronizing signal is missing from said input signal received in said receiving means; and an artificial synchronizing signal adding means for adding said artificial synchronizing signal to said input signal, said artificial synchronizing signal generating means including a first flip-flop circuit and a shift register, said first flip-flop circuit being actuated to a set condition by said synchronizing signal or said information signal from said receiving means and being actuated to a reset condition in response to the discrimination of said discriminating means, the shifting function of said shift register being controlled in response to outputs from said first flip-flop circuit, and the output signals from said shift register supplying said artificial synchronization signal.
Claim 2
Dependent Claim
173 words
A synchronizing signal reconstituting circuit which comprises: a receiving means for receiving an input signal including an information signal and a synchronizing signal having a constant period; a synchronizing signal discriminating means for discriminating said synchronizing signal in said input signal from said receiving means; an artificial synchronizing signal generating means for generating an artificial synchronizing signal when a synchronizing signal is missing from said input signal received in said receiving means; and an artificial synchronizing signal adding means for adding said artificial synchronizing signal to said input signal, said artificial synchronizing signal generating means including a first flip-flop circuit and a shift register, said first flip-flop circuit being actuated to a set condition by said synchronizing signal or said information signal from said receiving means and being actuated to a reset condition in response to the discrimination of said discriminating means, the shifting function of said shift register being controlled in response to outputs from said first flip-flop circuit, and the output signals from said shift register supplying said artificial synchronization signal.
Claim 3
Dependent Claim
82 words
The circuit as claimed in claim 1 wherein said artificial synchronizing signal generating circuit further comprises a NAND gate to which said synchronizing signal as well as said artificial synchronizing signal are applied and a second flip-flop circuit which is set by the output from said NAND gate, so that said shift register is controlled by the output of said second flip-flop circuit to correct the delay of the timing of said artificial synchronizing signal when said synchronizing signal is continuously missing.
Claim 4
Dependent Claim
51 words
The circuit as claimed in claim 1 further comprising a phase locked loop circuit coupled to be supplied with a synchronizing signal discriminated by said discriminating means as a reference signal so that the output of said phase locked loop circuit is applied to said shift register as a clock signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-08-14 | 1988-02-13 | 1988-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-08-14 | 1992-02-13 | 1992-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-08-14 | 1996-02-13 | 1996-08-14 | $7700.00 | Window Closed / Lapsed |