US4466012A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device with deep oxide isolation
Assignee: Fujitsu Ltd
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Filing: 1982-06-25
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Granted: 1984-08-14
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Expires: 2002-06-25
Abstract
Abstract A semiconductor device includes therein a plurality of semiconductor elements. First passive isolation regions are formed along the buried layer and second passive isolation regions are formed perpendicularly along the buried layer, enclosing each of the semiconductor elements, additional passive isolation regions are provided at the end portions of the second passive isolation regions wherever the first and second passive isolation regions merge. The additional passive isolation regions are deeper than the second passive isolation regions.
Inventors
- 👤 Toshitaka Fukushima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 03:20
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10P50/644; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
130 words
A semiconductor device having a plurality of semiconductor elements, comprising: a substrate; an epitaxial layer formed on said substrate; a buried layer of high conductivity, formed inside both said substrate and said epitaxial layer; a first passive isolation region formed parallel to said buried layer through said epitaxial layer and penetrating into said substrate; a second passive isolation region, having a center portion and end portions, formed perpendicular to said buried layer and said first passive isolation region and penetrating into said buried layer, said second passive isolation region formed in such a manner as to enclose, together with said first passive isolation region, each of the semiconductor elements, said end portions of said second passive isolation region being deeper than said center portion of said second passive isolation region.
Claim 2
Dependent Claim
130 words
A semiconductor device having a plurality of semiconductor elements, comprising: a substrate; an epitaxial layer formed on said substrate; a buried layer of high conductivity, formed inside both said substrate and said epitaxial layer; a first passive isolation region formed parallel to said buried layer through said epitaxial layer and penetrating into said substrate; a second passive isolation region, having a center portion and end portions, formed perpendicular to said buried layer and said first passive isolation region and penetrating into said buried layer, said second passive isolation region formed in such a manner as to enclose, together with said first passive isolation region, each of the semiconductor elements, said end portions of said second passive isolation region being deeper than said center portion of said second passive isolation region.
Claim 3
Dependent Claim
23 words
A semiconductor device as set forth in claim 1, wherein said end portions of said second passive isolation region penetrate into said substrate.
Claim 4
Dependent Claim
22 words
A semiconductor device as set forth in claim 1, wherein said first and second passive isolation regions are formed in V-shaped grooves.
Claim 5
Dependent Claim
30 words
A semiconductor device as set forth in claim 1, wherein the width of said end portions of said second passive isolation region is wider than that of said center portion.
Claim 6
Dependent Claim
42 words
A semiconductor device as set forth in claim 1, wherein each of said first and second passive isolation regions comprises a groove, an insulating film covering said groove, and a polycrystalline layer formed on said insulating film filling each of said grooves.
Claim 7
Dependent Claim
42 words
A semiconductor device as set forth in claim 1, wherein each of said first and second passive isolation regions comprise: a groove; an insulating film covering said groove; and a filling material, formed on said insulating film, filling each of said grooves.
Claim 8
Dependent Claim
90 words
A semiconductor device having a plurality of semiconductor elements, comprising: a substrate; an epitaxial layer formed on said substrate; a buried layer of high conductivity formed inside both said substrate and said epitaxial layer; a first passive isolation groove formed parallel to said buried layer through said epitaxial layer and penetrating said substrate; and a second passive isolation grove, having a center portion and end portions which penetrate into said substrate and are wider than said center portion, formed perpendicular to said buried layer and said first passive isolation groove.
Claim 9
Dependent Claim
90 words
A semiconductor device having a plurality of semiconductor elements, comprising: a substrate; an epitaxial layer formed on said substrate; a buried layer of high conductivity formed inside both said substrate and said epitaxial layer; a first passive isolation groove formed parallel to said buried layer through said epitaxial layer and penetrating said substrate; and a second passive isolation grove, having a center portion and end portions which penetrate into said substrate and are wider than said center portion, formed perpendicular to said buried layer and said first passive isolation groove.
Claim 10
Dependent Claim
35 words
A semiconductor device as set forth in claim 7, wherein said first passive isolation groove and said second passive isolation groove are formed in such a manner as to enclose each of the semiconductor elements.
Claim 11
Dependent Claim
39 words
A semiconductor device as set forth in claim 7, wherein said first and second passive isolation grooves are covered with an insulating film and a filling material is formed on said insulating film filling each of said isolation grooves.
Claim 12
Dependent Claim
36 words
A semiconductor device as set forth in claim 7, wherein said buried layer intersects said first passive isolation groove and has an upper edge that is removed by the formation of said second passive isolation groove.
Claim 13
Dependent Claim
19 words
A semiconductor device as set forth in claim 7, wherein said first and second passive isolation grooves are V-shaped.
Claim 14
Dependent Claim
17 words
A semiconductor device as set forth in claim 9, wherein said filling material comprises a polycrystalline layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-08-14 | 1988-02-13 | 1988-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-08-14 | 1992-02-13 | 1992-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-08-14 | 1996-02-13 | 1996-08-14 | $7700.00 | Window Closed / Lapsed |