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Method and apparatus for analyzing an analog-to-digital converter with a nonideal digital-to-analog converter

Assignee: National Semiconductor Corp
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Filing: 1982-04-01
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Granted: 1984-08-14
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Expires: 2002-04-01
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Abstract

Abstract A method for statistically calibrating an analog-to-digital converter with an electronic test system. A digital-to-analog converter which has been calibrated by premeasured weighting coefficients with respect to two-state orthogonal signals is excited with two state signals at each input bit which together represent a single signal with uniform amplitude probability with respect to time, and wherein each excitation signal is orthogonal with respect to all other excitation signals. The output of the digital-to-analog converter is detected by the analog-to-digital converter under test. The digital time domain output signals are then mapped into a transform domain to obtain weighting coefficients of each bit of the output response. Finally the transform domain weighting coefficients are weighted by the reciprocal of the premeasured weighting coefficients to obtain the unbiased weight of each bit of the analog-to-digital converter under test. A preferred set of excitation signals is a set of Walsh function signals representing the digital equivalent of a linear ramp function.

Inventors

  • 👤 Edwin A. Sloane

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 19:47
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/19; G01; G01R; G01R31/00; G01R31/28; H; H03; H03M; H03M1/00; H03M1/10; H03M1/1071

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 217 words
A method for calibrating an analog-to-digital converter (ADC) comprising the steps of: exciting a plurality of inputs of a digital-to-analog converter (DAC) from an excitation means generating known digital excitation signals, each said excitation signal being applied at a single digital bit input of the DAC and each said excitation signal being binary and orthogonal with respect to all other ones of said plurality of excitation signals, the sum of said excitation signals constituting a maximum extropy sequence of substantially uniform amplitude probability, said DAC producing an analog output signal, the transfer function of said DAC having been characterized by premeasured bit weighting values; providing said analog output signal of the DAC to an analog input of the analog-to-digital converter (ADC) under test, said ADC producing digital output signals; transforming said digital output signals from time domain digital signals into binary transform domain digital signals to obtain an output response weighting coefficient for each bit of the converter under test; and correcting each said output response weighting coefficient for bias errors induced by said DAC by multiplying each output response weighting coefficient by the reciprocal of each corresponding said premeasured bit weighting values in a bias correction means in order to obtain unbiased weighting values of each bit specifying the transfer characteristic of the ADC under test.
Claim 2
Independent Claim 217 words
A method for calibrating an analog-to-digital converter (ADC) comprising the steps of: exciting a plurality of inputs of a digital-to-analog converter (DAC) from an excitation means generating known digital excitation signals, each said excitation signal being applied at a single digital bit input of the DAC and each said excitation signal being binary and orthogonal with respect to all other ones of said plurality of excitation signals, the sum of said excitation signals constituting a maximum extropy sequence of substantially uniform amplitude probability, said DAC producing an analog output signal, the transfer function of said DAC having been characterized by premeasured bit weighting values; providing said analog output signal of the DAC to an analog input of the analog-to-digital converter (ADC) under test, said ADC producing digital output signals; transforming said digital output signals from time domain digital signals into binary transform domain digital signals to obtain an output response weighting coefficient for each bit of the converter under test; and correcting each said output response weighting coefficient for bias errors induced by said DAC by multiplying each output response weighting coefficient by the reciprocal of each corresponding said premeasured bit weighting values in a bias correction means in order to obtain unbiased weighting values of each bit specifying the transfer characteristic of the ADC under test.
Claim 3
Dependent Claim 15 words
The method according to claim 1 wherein the digital excitation signals are Walsh function signals.
Claim 4
Dependent Claim 22 words
The method according to claim 2 wherein the transforming step comprises transforming time domain digital signals into corresponding Walsh transform domain signals
Claim 5
Dependent Claim 21 words
The method according to claim 3 wherein said digital excitation signals comprise together a digital representation of a linear amplitude ramp.
Claim 6
Dependent Claim 66 words
The method according to claim 1 wherein the unbiased weighting coefficient of the m th bit of analog-to-digital converter under test is represented by: a.sub.m =a.sub.m k.sub.m where a m is the output response weighting coefficient of the m th bit; and k m is a coefficient based on the ideal output of said digital-to-analog converter and the corresponding premeasured weighting value of the digital-to-analog converter.
Claim 7
Independent Claim 224 words
An apparatus for calibrating an analog-to-digital converter (ADC) comprising: means for exciting inputs of a digital-to-analog converter (DAC) from an excitation means operative to generate known digital excitation signals at selected digital excitation signal outputs, each said excitation signal output being adapted to be coupled to a single digital bit input of the DAC under test and each said excitation signal constituting a maximum entropy sequence of substantially uniform amplitude probability, said DAC producing an analog output signal at an analog output signal terminal, the transfer function of said DAC having been characterized by premeasured weighting values of a set of binary orthogonal functions; the ADC under test adapted to be coupled to said DAC analog output signal terminal, said ADC under test being operative to produce digital output signals in response to said analog output signal; means for transforming said digital output signals from time domain digital signals into binary transform domain digital signals to obtain an output response weighting coefficient for each bit of the converter under test; and means for correcting each said output response weighting coefficient for bias errors induced by said DAC by multiplying each output response weighting coefficient by the reciprocal of each corresponding said premeasured weighting values in order to obtain unbiased weighting values of each bit specifying the transfer characteristic of the analog-to-digital converter under test.
Claim 8
Independent Claim 224 words
An apparatus for calibrating an analog-to-digital converter (ADC) comprising: means for exciting inputs of a digital-to-analog converter (DAC) from an excitation means operative to generate known digital excitation signals at selected digital excitation signal outputs, each said excitation signal output being adapted to be coupled to a single digital bit input of the DAC under test and each said excitation signal constituting a maximum entropy sequence of substantially uniform amplitude probability, said DAC producing an analog output signal at an analog output signal terminal, the transfer function of said DAC having been characterized by premeasured weighting values of a set of binary orthogonal functions; the ADC under test adapted to be coupled to said DAC analog output signal terminal, said ADC under test being operative to produce digital output signals in response to said analog output signal; means for transforming said digital output signals from time domain digital signals into binary transform domain digital signals to obtain an output response weighting coefficient for each bit of the converter under test; and means for correcting each said output response weighting coefficient for bias errors induced by said DAC by multiplying each output response weighting coefficient by the reciprocal of each corresponding said premeasured weighting values in order to obtain unbiased weighting values of each bit specifying the transfer characteristic of the analog-to-digital converter under test.
Claim 9
Dependent Claim 16 words
The apparatus according to claim 6 wherein said exciting means is a Walsh function signal generator.
Claim 10
Dependent Claim 24 words
The apparatus according to claim 7 wherein the transforming means comprises means for transforming time domain digital signals into corresponding Walsh transform domain signals.
Claim 11
Dependent Claim 21 words
The apparatus according to claim 8 wherein said digital excitation signals comprise together a digital representation of a linear amplitude ramp.
Claim 12
Dependent Claim 67 words
The apparatus according to claim 6 wherein said unbiased weighting coefficient of the m th bit of a digital-to-analog converter under test is represented by: a.sub.m =a.sub.m k.sub.m where a m is the output response weighting coefficient of the m th bit; and k m is a coefficient based on the ideal output of said digital-to-analog converter and the corresponding premeasured weighting value of the digital-to-analog converter.

References Cited (Backward Citations)

US4340856A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-08-14 1988-02-13 1988-08-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-08-14 1992-02-13 1992-08-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-08-14 1996-02-13 1996-08-14 $7700.00 Window Closed / Lapsed

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