Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
137 words
A method for detecting the absence or addition of a pulse in either of first and second pulse trains, the pulses of the first pulse train alternating, in time, with the pulses of the second pulse train, said method comprising the step of: providing a three-stage shift register capable of shifting bidirectionally; loading a 0 into the first stage of the shift register; loading a 1 into the third stage of the shift register; shifting the 0 loaded into said first stage toward said third stage with said first pulse train; shifting the 1 loaded into said third stage toward said first stage with said second pulse train; detecting the presence of like outputs from said first and third stages, and generating an output error signal when like outputs from said first and third stages are detected.
Claim 2
Independent Claim
137 words
A method for detecting the absence or addition of a pulse in either of first and second pulse trains, the pulses of the first pulse train alternating, in time, with the pulses of the second pulse train, said method comprising the step of: providing a three-stage shift register capable of shifting bidirectionally; loading a 0 into the first stage of the shift register; loading a 1 into the third stage of the shift register; shifting the 0 loaded into said first stage toward said third stage with said first pulse train; shifting the 1 loaded into said third stage toward said first stage with said second pulse train; detecting the presence of like outputs from said first and third stages, and generating an output error signal when like outputs from said first and third stages are detected.
Claim 3
Dependent Claim
36 words
The method as claimed in claim 1, wherein said detecting and generating step includes: inverting the output of said first stage and logically NANDing the inverted output so obtained with the output of said third stage.
Claim 4
Dependent Claim
29 words
The method as claimed in claim 1, wherein said detecting and generating step includes: generating a fixed width pulse coincident with the leading edge of said output error signal.
Claim 5
Dependent Claim
36 words
The method as claimed in claim 1, wherein said detecting and generating step includes: inverting the output of said third stage and logically ORing the inverted output so obtained with the output of said first stage.
Claim 6
Dependent Claim
145 words
A pulse drop-out detector for detecting the absence or addition of a pulse in either of first and second pulse trains, the pulses of the first pulse train alternating, in time, with the pulses of the second pulse train, comprising: a three-stage shift register capable of shifting bidirectionally; means for loading a 0 into the first stage of said shift register; means for loading a 1 into the third stage of said shift register; means for shifting the 0 loaded into said first stage toward said third stage with said first pulse train; means for shifting the 1 loaded into said third stage toward said first stage with said second pulse train; and means for detecting the presence of like outputs from said first and third stages, and for generating an output error signal when like outputs from said first and third stages are detected.
Claim 7
Dependent Claim
145 words
A pulse drop-out detector for detecting the absence or addition of a pulse in either of first and second pulse trains, the pulses of the first pulse train alternating, in time, with the pulses of the second pulse train, comprising: a three-stage shift register capable of shifting bidirectionally; means for loading a 0 into the first stage of said shift register; means for loading a 1 into the third stage of said shift register; means for shifting the 0 loaded into said first stage toward said third stage with said first pulse train; means for shifting the 1 loaded into said third stage toward said first stage with said second pulse train; and means for detecting the presence of like outputs from said first and third stages, and for generating an output error signal when like outputs from said first and third stages are detected.
Claim 8
Dependent Claim
44 words
The apparatus as claimed in claim 5, wherein said means for detecting and generating includes: an inverter for inverting the output of said first stage; and a NAND gate for logically NANDing the inverted output so obtained with the output of said third stage.
Claim 9
Dependent Claim
34 words
The apparatus as claimd in claim 5, wherein said means for detecting and generating includes: pulse generating means for generating a fixed width pulse coincident with the leading edge of said output error signal.
Claim 10
Dependent Claim
44 words
The apparatus as claimed in claim 5, wherein said means for detecting and generating includes: an inverter for inverting the output of said third stage; and an OR gate for logically ORing the inverted output so obtained with the output of said first stage.