US4439729A
Expired / Lapsed
US
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Evaluation circuit for a digital tachometer
Assignee: Siemens AG
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Filing: 1982-03-24
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Granted: 1984-03-27
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Expires: 2002-03-24
Abstract
Abstract An evaluation circuit for receiving the output signals from a tachometer, the output signal consisting of first and second speed-proportional pulse trains which are phase-shifted with respect to one another in response to the direction of rotation. The evaluation circuit converts the phase-shifted pulse trains into a speed-proportional pulse train having a frequency which is four times that of the first and second pulse trains, and into a separate sign signal indicative of the direction of rotation. The first and second pulse trains are conducted to respective first and second signal memories which are controlled by a clock signal. In one embodiment, four possible states for the combined first and second pulse trains are assigned respective designating numbers. The count in a bidirectional counter is caused to follow changes in the designating numbers, the bidirectional counter counting pulses from the clock signal until such coincidence is achieved. The pulses so counted represent the desired speed-proportional pulse train. The present evaluation circuit operates to produce correct speed-proportional and direction-indicating signals even where the pulses of the first and second pulse trains are in phase with one another.
Inventors
- 👤 Ulf Claussen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 11:51
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/02; G; G01; G01P; G01P13/00; G01P13/02; G01P13/04; G01P13/045
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
431 words
A evaluation circuit for a digital tachometer, the digital tachometer being of the type which produces first and second pulse trains having a frequency proportional to the speed of rotation, the pulse trains being phase-shifted in response to the direction of rotation, the evaluation circuit being of the type which converts the first and second pulse trains into a speed-proportional pulse train having four times the frequency of the first and second pulse train, and into a separate sign signal, the evaluation circuit further comprising: clock terminal means for receiving a clock signal having at least four times the maximum frequency of the first and second pulse trains; first and second signal memory means for receiving the first and second pulse trains, respectively, said first and second signal memory means being controlled by said clock signal, and producing at respective output terminals first and second memory means output signals, said memory means output signals, in combination, forming sequential binary numbers corresponding to predetermined combinations of the first and second pulse trains; controllable switch means having a first input terminal connected to said clock terminal means for receiving said clock signal, a second input terminal for receiving a controllable switch means enabling signal, and an output terminal for producing said clock signal in response to said controllable switch means enabling signal; bidirectional counter means having a first input terminal connected to said output terminal of said controllable switch means, for counting the negative flanks of said clock signal; comparator means having a plurality of input terminals connected to respective output terminals of said first and second signal memory means and said bidirectional counter means, said comparator means further having a plurality of output terminals, each output terminal producing a respective output signal indicative of a predetermined deviation from a prior sequential binary number formed from said memory means output signals, first and second ones of said plurality of output terminals corresponding to deviations of "+1" and "-1", respectively, said comparator means further having a third output terminal for producing a signal indicative of coincidence of a binary number at said output terminals of said bidirectional counter means and said sequential binary numbers formed of said memory means output signals, said third output terminal being connected to said second input terminal of said controllable switch means for producing said controllable switch means enabling signal; and sign means having first and second input terminals connected to said first and second output terminals, respectively, of said comparator means, and an output terminal for producing a signal indicative of the direction of rotation of the tachometer.
Claim 2
Dependent Claim
431 words
A evaluation circuit for a digital tachometer, the digital tachometer being of the type which produces first and second pulse trains having a frequency proportional to the speed of rotation, the pulse trains being phase-shifted in response to the direction of rotation, the evaluation circuit being of the type which converts the first and second pulse trains into a speed-proportional pulse train having four times the frequency of the first and second pulse train, and into a separate sign signal, the evaluation circuit further comprising: clock terminal means for receiving a clock signal having at least four times the maximum frequency of the first and second pulse trains; first and second signal memory means for receiving the first and second pulse trains, respectively, said first and second signal memory means being controlled by said clock signal, and producing at respective output terminals first and second memory means output signals, said memory means output signals, in combination, forming sequential binary numbers corresponding to predetermined combinations of the first and second pulse trains; controllable switch means having a first input terminal connected to said clock terminal means for receiving said clock signal, a second input terminal for receiving a controllable switch means enabling signal, and an output terminal for producing said clock signal in response to said controllable switch means enabling signal; bidirectional counter means having a first input terminal connected to said output terminal of said controllable switch means, for counting the negative flanks of said clock signal; comparator means having a plurality of input terminals connected to respective output terminals of said first and second signal memory means and said bidirectional counter means, said comparator means further having a plurality of output terminals, each output terminal producing a respective output signal indicative of a predetermined deviation from a prior sequential binary number formed from said memory means output signals, first and second ones of said plurality of output terminals corresponding to deviations of "+1" and "-1", respectively, said comparator means further having a third output terminal for producing a signal indicative of coincidence of a binary number at said output terminals of said bidirectional counter means and said sequential binary numbers formed of said memory means output signals, said third output terminal being connected to said second input terminal of said controllable switch means for producing said controllable switch means enabling signal; and sign means having first and second input terminals connected to said first and second output terminals, respectively, of said comparator means, and an output terminal for producing a signal indicative of the direction of rotation of the tachometer.
Claim 3
Dependent Claim
77 words
The evaluation circuit of claim 1 wherein said bidirectional counter means is a binary counter and there is further provided code converter means electrically interconnected intermediate of said output terminals of said first and second signal memory means and said comparator means, said code converter means being arranged to convert said sequential binary numbers formed of said memory means output signals into successive binary numbers corresponding to said predetermined combinations of the first and second pulse trains.
Claim 4
Dependent Claim
106 words
The evaluation circuit of claim 2 wherein said code converter means is provided with first and second input terminals connected to respectively associated ones of the output terminals of said signal memory means, said code converter means further having first and second output terminals, said first input and first output terminals of said code converter means being directly coupled to one another, said code converter means further having Exclusive-OR gate means having first and second input terminals connected to said first and second input terminals, respectively, of said code converter means, and an output terminal connected to said second output terminal of said code converter means.
References Cited (Backward Citations)
SU809483A1
Cited
US4403193A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-27 | 1987-09-26 | 1988-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-27 | 1991-09-26 | 1992-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-27 | 1995-09-26 | 1996-03-27 | $7700.00 | Window Closed / Lapsed |