US4464756A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for error detection in frequency shift keyed signals
Assignee: Honeywell Inc
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Filing: 1984-02-27
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Granted: 1984-08-07
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Expires: 2004-02-27
Abstract
Abstract An improved binary signal discrimination system for demodulating FSK transmitted signals is disclosed which requires that both the mark or binary "1" signal frequency and the complementary of the space or binary "0" frequency be present for a mark signal to be recognized; and, conversely requires that both the space signal frequency and the complement of the mark signal frequency be present for a space signal to be recognized.
Inventors
- 👤 Erik T. Tromborg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:58
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/02; H04L1/04
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
214 words
In an FSK receiver system having mark and space channels connected to a binary logic decision making system, the improvement comprising an essentially instantaneous validation system for checking the validity of any bit of a message or message unit, said validation system further comprising: first circuit means connected to said mark channel responsive to mark signals on said mark channel and having a characteristic output which is the complement of said mark signal; second circuit means connected to said space channel responsive to space signals on said space channel and having a characteristic output which is the complement of said space signal; first gate means connected to receive simultaneous inputs directly from both said mark channel and the output of said second circuit means, said first gate means adapted to generate a signal responsive only to the presence of both said mark signal and the complement of said space signal; second gate means connected to receive simultaneous inputs directly from both said space channel and said first circuit means, said second gate means being adapted to generate a signal responsive only to the presence of both said space signal and the complement of said mark signal; and means connecting the output of said first and said second gate means to a signal utilization means.
Claim 2
Dependent Claim
214 words
In an FSK receiver system having mark and space channels connected to a binary logic decision making system, the improvement comprising an essentially instantaneous validation system for checking the validity of any bit of a message or message unit, said validation system further comprising: first circuit means connected to said mark channel responsive to mark signals on said mark channel and having a characteristic output which is the complement of said mark signal; second circuit means connected to said space channel responsive to space signals on said space channel and having a characteristic output which is the complement of said space signal; first gate means connected to receive simultaneous inputs directly from both said mark channel and the output of said second circuit means, said first gate means adapted to generate a signal responsive only to the presence of both said mark signal and the complement of said space signal; second gate means connected to receive simultaneous inputs directly from both said space channel and said first circuit means, said second gate means being adapted to generate a signal responsive only to the presence of both said space signal and the complement of said mark signal; and means connecting the output of said first and said second gate means to a signal utilization means.
Claim 3
Dependent Claim
55 words
The apparatus of claim 1 further comprising, third gate means connected to receive simultaneous direct inputs from both said mark and said space channels, said third gate means being adapted to generate a signal only in the presence of both said mark and said space signals thereby indicating the presence of noise or false signals.
Claim 4
Independent Claim
67 words
The apparatus according to either of claims 1 or 2 further comprising, fourth gate means connected to receive simultaneous, direct inputs from the outputs of both said first and said second circuit means, said fourth gate means being adapted to generate a signal in response only to the absence of both said mark and said space signals in said channels thereby indicating the absence of a signal.
Claim 5
Independent Claim
27 words
The apparatus of any of claims 1 through 3 wherein said first and second circuit means are inverters and all of said gate means are AND gates.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-08-07 | 1988-02-06 | 1988-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-08-07 | 1992-02-06 | 1992-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-08-07 | 1996-02-06 | 1996-08-07 | $7700.00 | Window Closed / Lapsed |