US3869669A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for high frequency digital data transmission
Assignee: Unisys Corp
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Filing: 1973-09-04
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Granted: 1975-03-04
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Expires: 1993-09-04
Abstract
Abstract A system is disclosed for transmitting digital data at high frequencies which minimizes distortion of the transmitted signal. The system includes an encoding circuit for converting the bit pattern to be transmitted into an improved two-frequency differential signal wherein each bit is represented by at least one full cycle of the differential signal. The differential signal cycle for a zero is comprised of the sum of a bit signal representing a zero and the reciprocal of the bit signal delayed by one fourth of the bit cell and similarly a one is represented by the sum of the bit signal representing a one and the reciprocal of the bit signal also delayed by one fourth of a bit cell. In addition the system includes a receiver circuit for converting the two-frequency differential signal received over a transmission line into a signal directly representing the original bit pattern.
Inventors
- 👤 Cornelius Eldert
- 👤 Virgilio J Quiogue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 08:24
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/10
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
174 words
A high frequency digital data transmission system comprising: encoding means for converting a bit pattern into an improved two-frequency differential signal wherein each bit state is represented by at least one full cycle of said differential signal said differential signal cycle comprised of the sum of a bit signal and the reciprocal of said bit signal delayed by a predetermined portion of the cycle time said encoding means comprising: a clock for generating clock pulses; a first flip flOp responsive to the bit pattern and said clock; a second flip flop responsive to said first flip flop for producing a bit signal; a third flip flop responsive to said second flip flop for producing a delayed bit signal; interface means to apply the combination of said bit signal and the reciprocal of said delayed bit signal to said transmission means thereby forming said improved differential signal; a transmission means for transmitting said differential signal; and receiver means responsive to said transmission means for converting said differential signal into a signal representing said bit pattern.
Claim 2
Dependent Claim
174 words
A high frequency digital data transmission system comprising: encoding means for converting a bit pattern into an improved two-frequency differential signal wherein each bit state is represented by at least one full cycle of said differential signal said differential signal cycle comprised of the sum of a bit signal and the reciprocal of said bit signal delayed by a predetermined portion of the cycle time said encoding means comprising: a clock for generating clock pulses; a first flip flOp responsive to the bit pattern and said clock; a second flip flop responsive to said first flip flop for producing a bit signal; a third flip flop responsive to said second flip flop for producing a delayed bit signal; interface means to apply the combination of said bit signal and the reciprocal of said delayed bit signal to said transmission means thereby forming said improved differential signal; a transmission means for transmitting said differential signal; and receiver means responsive to said transmission means for converting said differential signal into a signal representing said bit pattern.
Claim 3
Dependent Claim
32 words
The high frequency digital data transmission system of claim 1 wherein said interface means further includes gating means for switching between a standard two-frequency differential signal and said improved two-frequency differential signal.
Claim 4
Dependent Claim
154 words
The high frequency digital data transmission system comprising: encoding means for converting a bit pattern into an improved two-frequency differential signal wherein each bit state is represented by at least one full cycle of said differential signal said differential signal cycle comprised of the sum of a bit signal and the reciprocal of said bit signal delayed by a predetermined portion of the cycle time; a transmission means for transmitting said differential signal; receiver means responsive to said transmission means for converting said differential signal into a signal pattern comprising: a first flip flop for receiving the differential signal from said transmission means; a delay element; a gating element for combining the output signal of said first flip flop and the output signal of said delay element; and a second flip flop responsive to the differential signal and the output signal of said gating element for producing a signal representative of the bit pattern.
Claim 5
Dependent Claim
154 words
The high frequency digital data transmission system comprising: encoding means for converting a bit pattern into an improved two-frequency differential signal wherein each bit state is represented by at least one full cycle of said differential signal said differential signal cycle comprised of the sum of a bit signal and the reciprocal of said bit signal delayed by a predetermined portion of the cycle time; a transmission means for transmitting said differential signal; receiver means responsive to said transmission means for converting said differential signal into a signal pattern comprising: a first flip flop for receiving the differential signal from said transmission means; a delay element; a gating element for combining the output signal of said first flip flop and the output signal of said delay element; and a second flip flop responsive to the differential signal and the output signal of said gating element for producing a signal representative of the bit pattern.
Claim 6
Dependent Claim
34 words
The high frequency digital data transmission system of claim 3 wherein said delay element includes a delay multivibrator for delaying the output of said first flip flop a predetermined proportion of a bit cell.
Claim 7
Dependent Claim
31 words
The high frequency digital data transmission system of claim 3 wherein said delay element includes elements for delaying the output of said first flip flop by three-eighths of a bit cell.
Claim 8
Dependent Claim
143 words
The high frequency digital data transmission system comprising: encoding means for converting a bit pattern into an improved two-frequency differential signal wherein each bit state is represented by at least one full cycle of said differential signal, said differential signal comprised of the sum of a bit signal and the reciprocal of said bit signal delayed by one fourth of a bit cell; transmission means for transmitting said differential signal; receiver means responsive to said transmission means for converting said differential signal into a signal representing said bit pattern; a first flip flop for receiving said differential signal from said transmission means; a delay circuit element; a gating element for combining the output of said first flip flop and the output of said delay circuit element; and a second flip flop responsive to said differential signal and the output of said gating element.
Claim 9
Dependent Claim
143 words
The high frequency digital data transmission system comprising: encoding means for converting a bit pattern into an improved two-frequency differential signal wherein each bit state is represented by at least one full cycle of said differential signal, said differential signal comprised of the sum of a bit signal and the reciprocal of said bit signal delayed by one fourth of a bit cell; transmission means for transmitting said differential signal; receiver means responsive to said transmission means for converting said differential signal into a signal representing said bit pattern; a first flip flop for receiving said differential signal from said transmission means; a delay circuit element; a gating element for combining the output of said first flip flop and the output of said delay circuit element; and a second flip flop responsive to said differential signal and the output of said gating element.
Claim 10
Dependent Claim
32 words
The high frequency digital data transmission system of claim 6 wherein said delay circuit element includes delay circuitry for delaying the output of said first flip flop three-eighths of a bit cell.
Claim 11
Dependent Claim
184 words
A high frequency digital data transmission system for transmitting an improved two-frequency differential signal comprising: clock means for generating a high frequency clock signal; a first flip flop responsive to a bit pattern and said clock means; a second flip flop responsive to said first flip flop for producing a bit signal; a third flip flop responsive to said second flip flop for producing a second bit signal delayed by a predetermined proportion of a bit cell; transmission means for receiving the output of said second flip flop and said third flip flop for transmitting the resultant differential signal; a first receive flip flop for receiving said differential signal from said transmission means; a delay circuit element including delay circuit elements for delaying the output of said first receive flip flop by a predetermined portion of a bit cell; a gating element for combining the output of said first receive flip flop and the output of said delay circuit element; and a second receive flip flop responsive to said differential signal and the output of said gating elements effective to reproduce the bit pattern.
Claim 12
Dependent Claim
184 words
A high frequency digital data transmission system for transmitting an improved two-frequency differential signal comprising: clock means for generating a high frequency clock signal; a first flip flop responsive to a bit pattern and said clock means; a second flip flop responsive to said first flip flop for producing a bit signal; a third flip flop responsive to said second flip flop for producing a second bit signal delayed by a predetermined proportion of a bit cell; transmission means for receiving the output of said second flip flop and said third flip flop for transmitting the resultant differential signal; a first receive flip flop for receiving said differential signal from said transmission means; a delay circuit element including delay circuit elements for delaying the output of said first receive flip flop by a predetermined portion of a bit cell; a gating element for combining the output of said first receive flip flop and the output of said delay circuit element; and a second receive flip flop responsive to said differential signal and the output of said gating elements effective to reproduce the bit pattern.
Claim 13
Dependent Claim
183 words
A high frequency digital data transmission system for encoding and receiving an improved differential signal comprising: encoding means for converting a bit pattern into an improved two-frequency differential signal wherein each bit state is represented by at least one full cycle of said differential signal, said differential signal comprised of the sum of a bit signal and the reciprocal of said bit signal delayed by one fourth of a bit cell said encoding means comprising: clock means for generating high frequency clock pulses; a first flip flop responsive to the bit pattern and said clock means; a second flip flop responsive to said first flip flop for producing said bit signal; a third flip flop responsive to said second flip flop for producing said bit signal delayed by one fourth of a bit cell; interface circuitry to apply the combination of said bit signal and the reciprocal of said delayed bit signal to said transmission means; transmission means for transmitting said differential signal; and receiver means responsive to said transmission means for converting said differential signal into a signal representing said bit pattern.
Claim 14
Dependent Claim
183 words
A high frequency digital data transmission system for encoding and receiving an improved differential signal comprising: encoding means for converting a bit pattern into an improved two-frequency differential signal wherein each bit state is represented by at least one full cycle of said differential signal, said differential signal comprised of the sum of a bit signal and the reciprocal of said bit signal delayed by one fourth of a bit cell said encoding means comprising: clock means for generating high frequency clock pulses; a first flip flop responsive to the bit pattern and said clock means; a second flip flop responsive to said first flip flop for producing said bit signal; a third flip flop responsive to said second flip flop for producing said bit signal delayed by one fourth of a bit cell; interface circuitry to apply the combination of said bit signal and the reciprocal of said delayed bit signal to said transmission means; transmission means for transmitting said differential signal; and receiver means responsive to said transmission means for converting said differential signal into a signal representing said bit pattern.
Claim 15
Dependent Claim
20 words
The high frequency digital data transmission system of claim 9 wherein said transmission means includes a balanced pair transmission line.
Claim 16
Dependent Claim
33 words
The high frequency digital data transmission system of claim 9 wherein said interface circuitry further includes a gating circuit for switching between a standard two-frequency differential signal and said improved two-frequency differential signal.
References Cited (Backward Citations)
US3801911A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-03-03 | 1978-09-02 | 1979-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-03-03 | 1982-09-02 | 1983-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-03-03 | 1986-09-02 | 1987-03-04 | $7700.00 | Window Closed / Lapsed |