In-package E2 PROM redundancy

Claim 2

A redundant memory circuit having a first and a second address terminal for providing at least one redundant memory element for a plurality of memory elements, comprising: a spare decoder coupled to said first and second address terminal; a row decoder coupled to said spare decoder for selecting word lines of said plurality of memory elements; a spare word line driver coupled to said spare decoder for selecting spare word lines of said plurality of memory elements; and programmable means coupled between said spare decoder and said first and second address terminals, for providing an output logically determined from a first address on said first address terminal and a second address on a said second address terminal wherein said programmable means is electronically programmable and electronically erasable in-package.

Claim 3

The redundant memory circuit according to claim 1 wherein said programmable means comprises: an output means coupled to said first and second address terminals for providing said output; programming voltage means coupled to said output means; and a floating gate E 2 PROM device coupled to said programming voltage means and said output means.

Claim 4

An address programming element for use in an E 2 PROM redundant memory circuit having at least two address conductors, a first write signal conductor, a second write signal conductor, a control gate conductor, a redundant ground conductor, and a programming voltage conductor for receiving a programming voltage, comprising: programmable means including an E 2 PROM device having a gate coupled to said control gate conductor, a first current conducting electrode coupled to said redundant ground conductor and a second current conducting electrode switchably coupled to said programming voltage conductor, said programmable means having at least a first and a second state, said first and said second state determined by the application of at least said programming voltage for providing a programmed signal; and output means coupled to said at least two address conductors and said programmable means, and responsive to said programmed signal for providing a logical output.

Claim 5

An address programming element for use in an E 2 PROM redundant memory circuit having at least two address conductors, a first write signal conductor, a second write signal conductor, a control gate conductor, a redundant ground conductor, and a programming voltage conductor for receiving a programming voltage, comprising: programmable means including an E 2 PROM device having a gate coupled to said control gate conductor, a first current conducting electrode coupled to said redundant ground conductor and a second current conducting electrode switchably coupled to said programming voltage conductor, said programmable means having at least a first and a second state, said first and said second state determined by the application of at least said programming voltage for providing a programmed signal; and output means coupled to said at least two address conductors and said programmable means, and responsive to said programmed signal for providing a logical output.

Claim 6

The address programming element according to claim 3 wherein said second current conducting electrode is further switchably coupled to at least one of said at least two address conductors.

Claim 7

The address programming element according to claim 4 wherein said output means comprises two differentially coupled transistors responsive to said programming means, for logically combining said at least two address conductors.

Claim 8

An address programming element for use in an E 2 PROM redundant memory circuit having at least two address conductors, a first write signal conductor, a second write signal conductor, a control gate conductor, a redundant ground conductor, a first reference conductor, a second reference conductor and a programming voltage conductor for receiving a programming voltage, comprising: a floating gate E 2 PROM device having a gate coupled to said control gate and a first current conducting electrode coupled to said redundant ground conductor; a first enhancement device having a gate coupled to said second write signal conductor and a first current conducting electrode coupled to a second current conducting electrode of said floating gate E 2 PROM device; a first depletion device having a first current conducting electrode coupled to said first reference conductor, and both a gate and a second current conducting electrode coupled to a second current conducting electrode of said first enhancement device; a first inverter having an input coupled to the second current conducting electrode of said first depletion device, and an output; a second inverter having an input coupled to said output of said first inverter; a first differentially connected enhancement device having a gate coupled to said output of said first inverter, a first current conducting electrode coupled to a first address conductor of said at least two address conductors, and a second current conducting electrode coupled to a logical output conductor; a second differentially coupled enhancement device having a gate coupled to said output of said second inverter, a first current conducting electrode coupled to a second address conductor of said at least two address conductors, and a second current conducting electrode coupled to said logical output conductor; a second depletion device having a gate coupled to said second write signal conductor, a first current conducting electrode coupled to said second address conductor; a third depletion device having a gate coupled to said first write signal conductor, a first current conducting electrode coupled to said programming voltage conductor, and a second current conducting electrode coupled to a second current conducting electrode of said second depletion device; a second enhancement device having a gate coupled to said second current conducting electrode of said third depletion device, a first current conducting electrode coupled to said programming voltage conductor; and a third enhancement device having a gate coupled to said second write signal conductor, a first current conducting electrode coupled to said second current conducting electrode of said second enhancement device, and a second current conducting electrode coupled to said second current conducting electrode of said floating gate E 2 PROM device.

Claim 9

An address programming element for use in an E 2 PROM redundant memory circuit having at least two address conductors, a first write signal conductor, a second write signal conductor, a control gate conductor, a redundant ground conductor, a first reference conductor, a second reference conductor and a programming voltage conductor for receiving a programming voltage, comprising: a floating gate E 2 PROM device having a gate coupled to said control gate and a first current conducting electrode coupled to said redundant ground conductor; a first enhancement device having a gate coupled to said second write signal conductor and a first current conducting electrode coupled to a second current conducting electrode of said floating gate E 2 PROM device; a first depletion device having a first current conducting electrode coupled to said first reference conductor, and both a gate and a second current conducting electrode coupled to a second current conducting electrode of said first enhancement device; a first inverter having an input coupled to the second current conducting electrode of said first depletion device, and an output; a second inverter having an input coupled to said output of said first inverter; a first differentially connected enhancement device having a gate coupled to said output of said first inverter, a first current conducting electrode coupled to a first address conductor of said at least two address conductors, and a second current conducting electrode coupled to a logical output conductor; a second differentially coupled enhancement device having a gate coupled to said output of said second inverter, a first current conducting electrode coupled to a second address conductor of said at least two address conductors, and a second current conducting electrode coupled to said logical output conductor; a second depletion device having a gate coupled to said second write signal conductor, a first current conducting electrode coupled to said second address conductor; a third depletion device having a gate coupled to said first write signal conductor, a first current conducting electrode coupled to said programming voltage conductor, and a second current conducting electrode coupled to a second current conducting electrode of said second depletion device; a second enhancement device having a gate coupled to said second current conducting electrode of said third depletion device, a first current conducting electrode coupled to said programming voltage conductor; and a third enhancement device having a gate coupled to said second write signal conductor, a first current conducting electrode coupled to said second current conducting electrode of said second enhancement device, and a second current conducting electrode coupled to said second current conducting electrode of said floating gate E 2 PROM device.

Claim 10

The redundant memory circuit according to claim 1 wherein said programmble means includes at least two address conductors, a first write signal conductor, a second write signal conductor, a control gate conductor, a redundant ground conductor, a first reference conductor, a second reference conductor and a programming voltage conductor for receiving a programming voltage, comprising: a floating gate E 2 PROM device having a gate coupled to said control gate and a first current conducting electrode coupled to said redundant ground conductor; a first enhancement device having a gate coupled to said second write signal conductor and a first current conducting electrode coupled to a second current conducting electrode of said floating gate E 2 PROM device; a first depletion device having a first current conducting electrode coupled to said first reference conductor, and both a gate and a second current conducting electrode coupled to a second current conducting electrode of said first enhancement device; a first inverter having an input coupled to said second current conducting electrode of said first depletion device, and an output; a second inverter having an input coupled to said output of said first inverter; a first differentially connected enhancement device having a gate coupled to said output of said first inverter, a first current conducting electrode coupled to a first address conductor of said at least two address conductors, and a second current conducting electrode coupled to a logical output conductor; a second differentially coupled enhancement device having a gate coupled to said output of said second inverter, a first current conducting electrode coupled to a second address conductor of said at least two address conductors, and a second current conducting electrode coupled to said logical output conductor; a second depletion device having a gate coupled to said second write signal conductor, a first current conducting electrode coupled to said second address conductor; a third depletion device having a gate coupled to said first write signal conductor, a first current conducting electrode coupled to said programming voltage conductor, and a second current conducting electrode coupled to a second current conducting electrode of said second depletion device; a second enhancement device having a gate coupled to said second current conducting electrode of said third depletion device, a first current conducting electrode coupled to said programming voltage conductor; and a third enhancement device having a gate coupled to said second write signal conductor, a first current conducting electrode coupled to said second current conducting electrode of said second enhancement device, and a second current conducting electrode coupled to said second current conducting electrode of said floating gate E 2 PROM device.