Semiconductor component

Claim 2

In a semiconductor circuit arrangement of the type in which a semiconductor component includes a semiconductor body which comprises a first base of a first conductivity type on a second base of a second conductivity type, a first emitter of the second conductivity type in the first base and having a surface coplanar with the boundary surface of the semiconductor body, a second emitter on the second base on the side opposite the first base, a first electrode on the first emitter and a second electrode on the second emitter for connection across an external circuit including a voltage source, and at least one metal-insulator-semiconductor controllable emitter short circuit including a gate electrode, said metal-insulator-semiconductor controllable emitter short circuit comprising a zone of second conductivity type in said first base extending up to the boundary surface and spaced from said first emitter, an edge portion of said first emitter, and the gate electrode carried on the boundary surface over respective sections of the zone and the edge portion and over the portion of the first base therebetween, the improvement therein comprising: a resistor including a first terminal connected to the first electrode and a second terminal for connection to the external circuit so that said resistor is in series with the component and the voltage source; and conductor means directly connecting said second terminal of said resistor to said gate electrode of said metal-insulator-semiconductor controllable emitter short circuit.

Claim 3

The improved semiconductor circuit arrangement of claim 1, wherein: said first emitter is of p conductivity.

Claim 4

The improved semiconductor circuit arrangement of claim 1, wherein: said first emitter is of n conductivity.

Claim 5

The improved semiconductor circuit arrangement of claim 1, wherein: the first emitter comprises a plurality of spaced apart emitter regions; the first electrode comprises a plurality of first electrode sections on respective emitter regions and each connected to the first terminal of said resistor; and a plurality of the metal-insulator-semiconductor controllable emitter short circuits for respective emitter regions, each including a gate electrode connected to said second terminal via said conductor means.

Claim 6

The improved semiconductor circuit arrangement of claim 1, and further comprising: a trigger electrode on one of the bases.

Claim 7

In a semiconductor circuit arrangement of the type in which a semiconductor component includes a semiconductor body which comprises a first base of a first conductivity type on a second base of a second conductivity type, a first emitter of the second conductivity type in the first base and having a surface coplanar with the boundary surface of the semiconductor body, a second emitter on the second base on the side opposite the first base, a first electrode on the first emitter and a second electrode on the second emitter for connection across an external circuit including a voltage source, and a metal-insulator-semiconductor controllable emitter short circuit including a gate electrode, a zone of the second conductivity type in the first base extending up to the boundary surface and spaced from the first emitter, an edge portion of the first emitter, and the gate electrode carried insulated on the boundary surface over respective sections of the zone and the edge portion and over the portion of the first base therebetween, the imporvement therein comprising: a resistor including a first terminal connected to the first electrode and a second terminal for connection to the external circuit so that said resistor is in series with the component and the voltage source; conductor means directly connecting said second terminal of said resistor to said gate electrode; the first emitter including two emitter regions in the first base, the gate electrode covering said edge portion of one of said emitter regions, an additional metal-insulator-semiconductor controllable emitter short circuit including an additional gate electrode carried insulated over the first base and covering a respective edge portion of the other emitter region for receiving a control voltage.

Claim 8

In a semiconductor circuit arrangement of the type in which a semiconductor component includes a semiconductor body which comprises a first base of a first conductivity type on a second base of a second conductivity type, a first emitter of the second conductivity type in the first base and having a surface coplanar with the boundary surface of the semiconductor body, a second emitter on the second base on the side opposite the first base, a first electrode on the first emitter and a second electrode on the second emitter for connection across an external circuit including a voltage source, and a metal-insulator-semiconductor controllable emitter short circuit including a gate electrode, a zone of the second conductivity type in the first base extending up to the boundary surface and spaced from the first emitter, an edge portion of the first emitter, and the gate electrode carried insulated on the boundary surface over respective sections of the zone and the edge portion and over the portion of the first base therebetween, the imporvement therein comprising: a resistor including a first terminal connected to the first electrode and a second terminal for connection to the external circuit so that said resistor is in series with the component and the voltage source; conductor means directly connecting said second terminal of said resistor to said gate electrode; the first emitter including two emitter regions in the first base, the gate electrode covering said edge portion of one of said emitter regions, an additional metal-insulator-semiconductor controllable emitter short circuit including an additional gate electrode carried insulated over the first base and covering a respective edge portion of the other emitter region for receiving a control voltage.

Claim 9

The improved semiconductor circuit arrangement of claim 6, and further comprising: a trigger electrode carried on one of the base layers and connected to said additional gate electrode.

Claim 10

A semiconductor circuit arrangement comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type adjacent said first semiconductor layer; a first zone of semiconductor material in said first layer and having the second conductivity type; a third semiconductor layer of the first conductivity type adjacent said second layer; a second zone of semiconductor material in said third layer and having the second conductivity type; first and second electrodes on said first zone and first layer and on said second zone and said third layer, respectively, for connection to an external voltage source; first and second metal-insulator-semiconductor controllable short circuits each including respective portions of said first zone and first layer and said second zone and said third layer, and a futher zone of the second conductivity type in the respective first and third layer and spaced from the first and second zones, and each including an insulated gate electrode bridging said zones in said first and third layers, respectively; and first and second resistors each including a first terminal connected to said first and second electrodes, respectively, and a second terminal directly connected to the respective gate electrode, said resistors being connected in an external circuit which includes the external voltage source.

Claim 11

A semiconductor circuit arrangement comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type adjacent said first semiconductor layer; a first zone of semiconductor material in said first layer and having the second conductivity type; a third semiconductor layer of the first conductivity type adjacent said second layer; a second zone of semiconductor material in said third layer and having the second conductivity type; first and second electrodes on said first zone and first layer and on said second zone and said third layer, respectively, for connection to an external voltage source; first and second metal-insulator-semiconductor controllable short circuits each including respective portions of said first zone and first layer and said second zone and said third layer, and a futher zone of the second conductivity type in the respective first and third layer and spaced from the first and second zones, and each including an insulated gate electrode bridging said zones in said first and third layers, respectively; and first and second resistors each including a first terminal connected to said first and second electrodes, respectively, and a second terminal directly connected to the respective gate electrode, said resistors being connected in an external circuit which includes the external voltage source.