Amplifier incorporating gain distribution control for cascaded amplifying stages

Claim 2

An amplifier comprising, in combination: first and second signal amplifying stages connected in cascade; and means coupled to said first and second signal amplifying stages for simultaneously varying the respective gains of said first and second signal amplifying stages in mutually opposite directions in such manner as to alter the distribution of gain between said stages substantially without disturbance of the overall gain of said amplifier.

Claim 3

Apparatus in accordance with claim 1, including a source of DC bias voltage, wherein said first signal amplifying stage derives its operating current from the collector electrode of a first current source transistor; said second signal amplifying stage derives its operating current from the collector electrode of a second current source transistor; and the base-emitter paths of said first and second current source transistors are connected in series-aiding relationship across said source of DC bias voltage; and wherein said gain varying means comprises a variable DC impedance coupled across the base-emitter path of one of said current source transistors.

Claim 4

An amplifier subject to gain distribution variation, comprising, in combination: first and second signal amplifying stages connected in cascade; first and second transistors, each having a base electrode; said first signal amplifying stage deriving its operating current from the collector electrode of said first transistor, and said second signal amplifying stage deriving its operating current from the collector electrode of said second transistor; a source of DC bias voltage; means for forward biasing the base-emitter junctions of said first and second transistors, said biasing means comprising means for connecting the base-emitter paths of said first and second transistors in series-aiding relationship across said bias voltage source; and a variable DC impedance coupled across the base-emitter path of one of said transistors.

Claim 5

An amplifier subject to gain distribution variation, comprising, in combination: first and second signal amplifying stages connected in cascade; first and second transistors, each having a base electrode; said first signal amplifying stage deriving its operating current from the collector electrode of said first transistor, and said second signal amplifying stage deriving its operating current from the collector electrode of said second transistor; a source of DC bias voltage; means for forward biasing the base-emitter junctions of said first and second transistors, said biasing means comprising means for connecting the base-emitter paths of said first and second transistors in series-aiding relationship across said bias voltage source; and a variable DC impedance coupled across the base-emitter path of one of said transistors.

Claim 6

An amplifier subject to gain distribution variation comprising in combination: first and second signal amplifying stages connected in cascade; first and second transistors, each having a base electrode, an emitter electrode and a collector electrode; said first signal amplifying stage deriving its operating current from the collector electrode of said first transistor, and said second signal amplifying stage deriving its operating current from the collector electrode of said second transistor; a source of DC bias voltage; means for forward biasing the base-emitter junctions of said first and second transistors, said biasing means comprising means for connecting the base-emitter paths of said first and second transistors in series across said bias voltage source; and a variable DC impedance coupled across the base-emitter path of one of said transistors; wherein said variable DC impedance comprises a third transistors; wherein said variable DC impedance comprises a third transistor having base, emitter and collector electrodes; the collector-emitter path of said third transistor being connected in shunt with the base-emitter path of said one transistor.

Claim 7

An amplifier subject to gain distribution variation comprising in combination: first and second signal amplifying stages connected in cascade; first and second transistors, each having a base electrode, an emitter electrode and a collector electrode; said first signal amplifying stage deriving its operating current from the collector electrode of said first transistor, and said second signal amplifying stage deriving its operating current from the collector electrode of said second transistor; a source of DC bias voltage; means for forward biasing the base-emitter junctions of said first and second transistors, said biasing means comprising means for connecting the base-emitter paths of said first and second transistors in series across said bias voltage source; and a variable DC impedance coupled across the base-emitter path of one of said transistors; wherein said variable DC impedance comprises a third transistors; wherein said variable DC impedance comprises a third transistor having base, emitter and collector electrodes; the collector-emitter path of said third transistor being connected in shunt with the base-emitter path of said one transistor.

Claim 8

Apparatus in accordance with claim 4 also including: a diode connected in shunt with the base-emitter path of said third transistor; a variable DC voltage source; and means, including a resistor, for providing a direct current conductive coupling between the base electrode of said third transistor and said variable DC voltage source.

Claim 9

Apparatus in accordance with claim 5 wherein said bias voltage source comprises a plurality of serially connected semiconductor junctions, with the series combination of a second resistor and a source of DC potential connected in shunt with said plurality of serially connected semiconductor junctions.

Claim 10

Apparatus in accordance with claim 6 wherein said first signal amplifying stage comprises fourth and fifth transistors, each having base, emitter and collector electrodes; with the emitter electrodes of said fourth and fifth transistors connected in common to the collector electrode of said first transistor; and wherein said second signal amplifying stage comprises sixth and seventh transistors, each having base, emitter and collector electrodes, with the emitter electrodes of said sixth and seventh transistors connected in common to the collector electrode of said second transistor.

Claim 11

Apparatus in accordance with claim 7 wherein a source of signals to be amplified is coupled between the base electrodes of said fourth and fifth transistors; wherein the base electrodes of said sixth and seventh transistors are driven in push-pull by amplified signals appearing at the collector electrodes of said fourth and fifth transistors; and wherein push-pull output signals are derived from the collector electrodes of said sixth and seventh transistors.

Claim 12

Apparatus in accordance with claim 8 wherein said one transistors is said first transistor, and wherein said second resistor is connected between said DC potential source and the base electrode of said second transistor.

Claim 13

An amplifier subject to gain distribution variation, comprising, in combination: first and second signal amplifying stages connected in cascade; first and second transistors of like conductivity type, each having base, emitter and collector electrodes; said first signal amplifying stage deriving its operating current from the collector electrode of said first transistor, and said second signal amplifying stage deriving its operating current from the collector electrode of said second transistor; a source of DC bias voltage; means for forward biasing the base-emitter junctions of said first and second transistors, said biasing means comprising means, including a direct connection between the emitter electrode of one of said first and second transistors and the base electrode of the other of said first and second transistors, for connecting the base-emitter paths of said first and second transistors in series-aiding relationship across said bias voltage source; a third transistor having base, emitter and collector electrodes; the collector-emitter path of said third transistor being connected in shunt with the base-emitter path of said other of said first and second transistors; and means for varying the biasing of the base-emitter path of said third transistor so as to cause opposite variations in said operating currents in such manner as to alter the distribution of gain between said first and second amplifying stages substantially without disturbance of the overall gain of said amplifier.

Claim 14

An amplifier subject to gain distribution variation, comprising, in combination: first and second signal amplifying stages connected in cascade; first and second transistors of like conductivity type, each having base, emitter and collector electrodes; said first signal amplifying stage deriving its operating current from the collector electrode of said first transistor, and said second signal amplifying stage deriving its operating current from the collector electrode of said second transistor; a source of DC bias voltage; means for forward biasing the base-emitter junctions of said first and second transistors, said biasing means comprising means, including a direct connection between the emitter electrode of one of said first and second transistors and the base electrode of the other of said first and second transistors, for connecting the base-emitter paths of said first and second transistors in series-aiding relationship across said bias voltage source; a third transistor having base, emitter and collector electrodes; the collector-emitter path of said third transistor being connected in shunt with the base-emitter path of said other of said first and second transistors; and means for varying the biasing of the base-emitter path of said third transistor so as to cause opposite variations in said operating currents in such manner as to alter the distribution of gain between said first and second amplifying stages substantially without disturbance of the overall gain of said amplifier.