Patent US4463439A successfully refreshed from Google Patents.
US4463439A
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Sum and carry outputs with shared subfunctions
Assignee: International Business Machines Corp
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Filing: 1982-05-17
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Granted: 1984-07-31
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Expires: 2002-05-17
Abstract
Abstract Full adder stages in this adder are made up of two half adder stages that will produce either the true or complement of the sum as a bundle of subfunction signals that can be shared between the sum and carry outputs of the full adder stage. The half adder stages come in a variety of forms to accommodate both true, both complement or one true and one complement input combinations to the stage.
Inventors
- 👤 Arnold Weinberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 12:35
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/53; G06F7/5306; G06F7/5312; G06F7/50; G06F7/501; G06F7/502; G06F7/505; G06F7/509; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
211 words
An adder of the type where sum and carry functions are produced by a plurality of individual full adder stages, which comprise: (a) first half adder type means for producing a partial sum as a bundle of subfunction signals one being a subfunction of the trues and the other a subfunction of the complements of two inputs when those inputs are both true or both complements, (b) second half adder type means for producing a partial sum as a bundle of subfunction signals one being said subfunction of the trues and the other said subfunction of the complements of said two inputs when those inputs are not both true or both complement, (c) full adder stage means including one of said half adder type means as a first half adder stage said full adder stage means generating full sum functions as a bundle of subfunction signals and full carry functions as a bundle of subfunction signals wherein the full carry functions include a subfunction signal of the other of said half adder type means and subfunction signal of said full sum function bundle, and (d) means for transmitting said full sum and carry functions of an adder stage each as a bundle of such subfunction signals to other full adder stages.
Claim 2
Dependent Claim
211 words
An adder of the type where sum and carry functions are produced by a plurality of individual full adder stages, which comprise: (a) first half adder type means for producing a partial sum as a bundle of subfunction signals one being a subfunction of the trues and the other a subfunction of the complements of two inputs when those inputs are both true or both complements, (b) second half adder type means for producing a partial sum as a bundle of subfunction signals one being said subfunction of the trues and the other said subfunction of the complements of said two inputs when those inputs are not both true or both complement, (c) full adder stage means including one of said half adder type means as a first half adder stage said full adder stage means generating full sum functions as a bundle of subfunction signals and full carry functions as a bundle of subfunction signals wherein the full carry functions include a subfunction signal of the other of said half adder type means and subfunction signal of said full sum function bundle, and (d) means for transmitting said full sum and carry functions of an adder stage each as a bundle of such subfunction signals to other full adder stages.
Claim 3
Dependent Claim
30 words
The adder of claim 1 wherein all half adder type means in said full adder stage means include two standard logic blocks with their outputs cross connected to generate subfunctions.
Claim 4
Dependent Claim
82 words
The adder of claim 2 wherein the input of one of said standard logic blocks in the first half adder type means of said full adder stage means is connected to the partial sum bundle of said other half adder stages means to receive the subfunction signals of said other half adder type means and the input to the other of said standard logic blocks in said first half adder type means receives a carry signal from another full adder stage means.
Claim 5
Dependent Claim
39 words
The adder of claim 2 wherein said half adder type means generate the product of the trues of the inputs and the product of the complement of the inputs as the subfunction signals in said partial sum output bundle.
Claim 6
Dependent Claim
17 words
The adder of claim 2 wherein said standard logic blocks perform an OR and a NOR function.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-31 | 1988-01-30 | 1988-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-31 | 1992-01-30 | 1992-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-31 | 1996-01-30 | 1996-07-31 | $7700.00 | Window Closed / Lapsed |