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US4462091A
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Word group redundancy scheme
Assignee: International Business Machines Corp
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Filing: 1982-02-26
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Granted: 1984-07-24
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Expires: 2002-02-26
Abstract
Abstract A word redundancy scheme for a high speed RAM where the bit output stage uses on-chip logic. An extra emitter on each of the decoders is utilized including redundant word group decoders. A compare circuit has an output to each of the extra emitters and when the address of a bad bit arrives at the compare circuit it de-selects each of the non-redundant decoders at that address and selects the redundant decoders via the extra emitters. Hence, the redundant decoders replace the decoders of the bad bit position.
Inventors
- 👤 Ronald W. Knepper
- 👤 Peter J. Ludlow
- 👤 Joseph A. Petrosky, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:40
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/781
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
150 words
A word redundancy scheme for a random access memory arrangement wherein the bit output stage uses on-chip logic, comprising: an array of word group decoders for a non-redundant portion of said memory and an array including at least one word group decoder for a redundant portion of said memory, each having an additional emitter; a compare circuit having input means and output means; means coupled to said compare circuit input means for applying a first set of address inputs representing word decoder locations in said non-redundant portion to be accessed, and a second set of address inputs representing defective bit address locations in said non-redundant memory portion; and means coupling said compare circuit output means to each of said additional emitters wherein when said first and said second sets of address inputs coincide, said decoders for a non-redundant portion are deselected and said decoders for said redundant portion are selected.
Claim 2
Dependent Claim
150 words
A word redundancy scheme for a random access memory arrangement wherein the bit output stage uses on-chip logic, comprising: an array of word group decoders for a non-redundant portion of said memory and an array including at least one word group decoder for a redundant portion of said memory, each having an additional emitter; a compare circuit having input means and output means; means coupled to said compare circuit input means for applying a first set of address inputs representing word decoder locations in said non-redundant portion to be accessed, and a second set of address inputs representing defective bit address locations in said non-redundant memory portion; and means coupling said compare circuit output means to each of said additional emitters wherein when said first and said second sets of address inputs coincide, said decoders for a non-redundant portion are deselected and said decoders for said redundant portion are selected.
Claim 3
Dependent Claim
31 words
The redundancy scheme of claim 1 wherein said first set of address inputs are received from address receivers and said second set of address inputs are personalized signals for the chip.
Claim 4
Dependent Claim
48 words
The redundancy scheme of claim 2 wherein said non-redundant memory portion comprises eight groups of sixteen words each and said redundant memory portion comprises sixteen words, and wherein when said plurality of word decoders are deselected in a group said redundant memory portion replaces one groups of words.
Claim 5
Dependent Claim
43 words
The redundancy scheme of claim 1 further comprising a disable input to said compare circuit wherein when said disable input is active said compare circuit is rendered to a non-compare state to disable said redundant memory portion and enalbe said non-redundant memory portion.
Claim 6
Dependent Claim
31 words
The redundancy scheme of claim 1 wherein said first set of address inputs are received from chip inputs and said second set of address inputs are programmed into shift register latches.
Claim 7
Dependent Claim
30 words
The redundancy scheme of claim 5 wherein said non-redundant memory portion comprises sixteen groups of eight words each and said redundant memory comprises at least one group of eight words.
Claim 8
Dependent Claim
25 words
The redundancy scheme of claims 2, 4 or 5 wherein said non-redundant memory portion, said redundant memory portion, and said compare circuit are disposed on-chip.
References Cited (Backward Citations)
US4346459A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-24 | 1988-01-23 | 1988-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-24 | 1992-01-23 | 1992-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-24 | 1996-01-23 | 1996-07-24 | $7700.00 | Window Closed / Lapsed |