Nonvolatile semiconductor memory device

Claim 1

A nonvolatile semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; two impurity regions of a second conductivity type formed in said semiconductor substrate spaced apart from each other; a floating gate of a semiconductor formed above said semiconductor substrate and between said two impurity regions, said floating gate being insulated from said semiconductor substrate and comprising first and second conductive regions having conductivity types opposite to each other and providing a junction therebetween; a first control gate formed above said first conductive region of said floating gate and insulated therefrom; a second control gate formed above said second conductive region of said floating gate and insulated from said floating gate and said first control gate; writing and erasing means for applying write voltages to said first and second control gates and said impurity regions to cause avalanche breakdown in said substrate so that hot carriers reach said first region of said floating gate for writing information, and for applying pulse-trains of an erase voltage to said first control gate while grounding said second control gate to cause avalanche breakdown in said floating gate so that hot carriers cross said junction and reach said first control gate for erasing said information; and said second control gate having a portion which rises up and over an edge of a portion of said first control gate that is over said first conductive region in the vicinity of said junction.