Bus request buffer circuit for interfacing between field maintenance processor and device specific adaptor

Claim 1

In a system including a data bus and first and second circuits each capable of exerting control over said data bus, a first bus request conductor coupled to a first bus request terminal of said first circuit and a second bus request conductor coupled to a second bus request terminal of said second circuit, said first circuit producing a logical "one" level on said first bus request terminal when said first circuit asserts control over said data bus, said second circuit producing a logical "one" level on said second bus request terminal when said second circuit asserts control over said data bus, said first circuit including means to monitor the level of said first bus request terminal and determine that there is a logical "zero" level thereon before asserting control over said data bus, said first circuit producing no output signal indicative of whether said first circuit is driving or monitoring said first bus request terminal on any terminal other than said first bus request terminal, a buffer circuit for interfacing between said first and second circuits comprising in combination: (a) flip-flop means for storing a logical "one" in response to a set signal and a logical "zero" in response to a reset signal, said flip-flop means having a set input and a reset input; (b) first logic gate circuit means having a first input coupled to said first bus request conductor and a second input coupled to said second bus request conductor for producing said reset signal on the condition that said first bus request conductor is at a logical "zero" level and said second bus request conductor goes from a logical "zero" level to a logical "one" level as said second circuit asserts control over said data bus; (c) means for coupling said first logic gate circuit means to said reset input to effect transmission of said reset signal to said reset input; (d) means coupling said first bus request conductor to said set input for applying a set signal to said set input when said first bus request conductor goes from a logical "one" level to a logical "zero" level as said first circuit stops asserting control over the data bus; (e) second logic gate means coupled to a first output of said flip-flop means for producing a logical "one" level on said second bus request conductor when a logical "one is stored in said flip-flop means and no circuit is asserting control over said data bus; (f) third logic gate means coupled to a second output of said flip-flop means and said first bus request conductor for producing a logical "one" on said first bus request conductor on the condition that a logical "one" is stored in said flip-flop means and a logical "one" is produced on said second bus request conductor as said second circuit asserts control over said data bus.