US4460972A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single chip microcomputer selectively operable in response to instructions stored on the computer chip or in response to instructions stored external to the chip
Assignee: International Business Machines Corp
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Filing: 1981-07-30
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Granted: 1984-07-17
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Expires: 2001-07-30
Abstract
Abstract A microprocessor external instruction feature which provides for a single chip microprocessor with on-chip read only instruction store (ROS) that can also be operated with an off-chip instruction store. To accomplish this, the microprocessor instruction sequencing logic (instruction store, instruction register, instruction counter, and sequencing logic) is duplicated off-chip. An XI MODE input pin signal causes the microprocessor to take its instructions from the external instruction store via 12 XI input pins instead of from the on-chip ROS. A BR DECISION output pin signal from the microprocessor, which indicates that the branch conditions have been met, causes the external instruction counter to be loaded with a branch address from the external instruction register instead of being stepped by external sequencing logic. A WAIT output pin signal causes the external instruction feature logic to suspend operations while the microprocessor is in its wait state.
Inventors
- 👤 Merle E. Homan
- 👤 Guenther K. Machol
- 👤 Larry M. Warren
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 06:48
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7864
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
241 words
Microcomputing apparatus, comprising a single chip microprocessor; a first instruction store on said single chip microprocessor for storing a first series of instructions to control operation of the apparatus; a first instruction register on said single chip microprocessor coupled to selectively receive instructions read out from said first instruction store or from a second instruction store; a first instruction address generating means on said single chip microprocessor for generating a first address for addressing said first instruction store to cause an instruction to be read out of said first instruction store; a second instruction store external to said single chip microprocessor for storing a second series of instructions to control operation of the apparatus; an external instruction counter external to said single chip microprocessor for generating a second address for addressing said second instruction store to cause an instruction to be read out of said second instruction store; and instruction mode means responsive to a first signal on said single chip microprocessor, said first signal having a first state specifying internal mode and a second state specifying external mode, said instruction mode means including means responsive to a specified internal mode for loading into said first instruction register the instruction read from said first instruction store in response to said first address and responsive to a specified external mode for loading into said first instruction register the instruction read out from said second instruction store in response to said second address.
Claim 2
Dependent Claim
241 words
Microcomputing apparatus, comprising a single chip microprocessor; a first instruction store on said single chip microprocessor for storing a first series of instructions to control operation of the apparatus; a first instruction register on said single chip microprocessor coupled to selectively receive instructions read out from said first instruction store or from a second instruction store; a first instruction address generating means on said single chip microprocessor for generating a first address for addressing said first instruction store to cause an instruction to be read out of said first instruction store; a second instruction store external to said single chip microprocessor for storing a second series of instructions to control operation of the apparatus; an external instruction counter external to said single chip microprocessor for generating a second address for addressing said second instruction store to cause an instruction to be read out of said second instruction store; and instruction mode means responsive to a first signal on said single chip microprocessor, said first signal having a first state specifying internal mode and a second state specifying external mode, said instruction mode means including means responsive to a specified internal mode for loading into said first instruction register the instruction read from said first instruction store in response to said first address and responsive to a specified external mode for loading into said first instruction register the instruction read out from said second instruction store in response to said second address.
Claim 3
Dependent Claim
52 words
The apparatus of claim 1, further comprising means for generating a second signal on said single chip microprocessor responsive to execution of a branch instruction on said single chip mircroprocessor with branch conditions met, and means for coupling said second signal to said external instruction counter for altering said external instruction counter.
Claim 4
Dependent Claim
23 words
The apparatus of claim 1 wherein the storage capacity of said second instruction store exceeds the storage capacity of said first instruction store.
Claim 5
Independent Claim
77 words
The apparatus of claims 1 additionally comprising external mode terminal means on said single microprocessor chip, means for coupling said instruction read out of said second instruction store in response to said external instruction counter to said external mode terminal means; and means for coupling said instruction read out of said second instruction store from said external mode terminal means to said first instruction register in response to said first signal having a state specifying external mode.
Claim 6
Dependent Claim
277 words
Microcomputing apparatus, comprising a single chip microprocessor a first instruction store on said single chip microprocessor for storing a first series of instructions to control operation of the apparatus; a first instruction register on said single chip microprocessor coupled to selectively receive instructions read out from said instruction store or from external instruction mode terminal means; a first instruction address generating means on said single chip microprocessor for generating a first address for addressing said first instruction store to cause an instruction to be read out of said first instruction store; external instruction mode terminal means on said single chip microprocessor accessible to an external source of signals; a second instruction store external to said single chip microprocessor for storing a second series of instructions to control operation of the apparatus; an external instruction counter external to said single chip microprocessor for generating a second address for addressing said second instruction store to cause an instruction to be read out of said second instruction store; and instruction mode means on said single chip microprocessor selectively specifying internal mode in response to a first signal having a first digital state at said external instruction mode terminal means for loading said first instruction register with the instruction read out from said first instruction store in response to the address from said first instruction address generating means and specifying external mode in response to said first signal having a digital state opposite to said first digital state at said external instruction mode terminal means for loading said first instruction register with the instruction read out from said second instruction store in response to the address from said external instruction counter.
Claim 7
Dependent Claim
277 words
Microcomputing apparatus, comprising a single chip microprocessor a first instruction store on said single chip microprocessor for storing a first series of instructions to control operation of the apparatus; a first instruction register on said single chip microprocessor coupled to selectively receive instructions read out from said instruction store or from external instruction mode terminal means; a first instruction address generating means on said single chip microprocessor for generating a first address for addressing said first instruction store to cause an instruction to be read out of said first instruction store; external instruction mode terminal means on said single chip microprocessor accessible to an external source of signals; a second instruction store external to said single chip microprocessor for storing a second series of instructions to control operation of the apparatus; an external instruction counter external to said single chip microprocessor for generating a second address for addressing said second instruction store to cause an instruction to be read out of said second instruction store; and instruction mode means on said single chip microprocessor selectively specifying internal mode in response to a first signal having a first digital state at said external instruction mode terminal means for loading said first instruction register with the instruction read out from said first instruction store in response to the address from said first instruction address generating means and specifying external mode in response to said first signal having a digital state opposite to said first digital state at said external instruction mode terminal means for loading said first instruction register with the instruction read out from said second instruction store in response to the address from said external instruction counter.
Claim 8
Dependent Claim
52 words
The apparatus of claim 5, further comprising means for generating a second signal on said single chip microprocessor responsive to execution of a branch instruction on said single chip microprocessor with branch conditions met, and means for coupling said second signal to said external instruction counter for altering said external instruction counter.
Claim 9
Dependent Claim
23 words
The apparatus of claim 5 wherein the storage capacity of said second instruction store exceeds the storage capacity of said first instruction store.
Claim 10
Dependent Claim
82 words
The apparatus of claim 5 additionally comprising external mode terminal means on said single microprocessor chip, means for coupling said instruction read out of said second instruction store in response to the address generated in said external instruction counter to said external mode terminal means; and means for coupling said instruction read out of said second instruction store from said external mode terminal means to said first instruction register in response to said first signal having a digital state specifying external mode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-17 | 1988-01-16 | 1988-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-17 | 1992-01-16 | 1992-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-17 | 1996-01-16 | 1996-07-17 | $7700.00 | Window Closed / Lapsed |