Semiconductor device

Claim 2

A semiconductor device having normal and test modes, comprising: an internal circuit for generating at least one internal signal; means for generating a reference signal; means, operatively connected to said internal circuit and to said reference signal generating means, for sensing the difference in potential between said internal signal and said reference signal; and means for changing the difference in potential between said internal signal and said reference signal, where the difference in the normal mode is different from that in the test mode.

Claim 3

A semiconductor device as set forth in clam 1, wherein said changing means comprises means, operatively connected to said reference signal generating means, for decreasing the potential of said reference signal in the test mode, rather than in the normal mode.

Claim 4

A semiconductor device as set forth in clam 1, wherein said changing means comprises means, operatively connected to said reference signal generating means, for decreasing the potential of said reference signal in the test mode, rather than in the normal mode.

Claim 5

A semiconductor device as set forth in claim 1, wherein said changing means comprises means, operatively connected to said internal circuit, for increasing the potential of said internal signal in the test mode, rather than in the normal mode.

Claim 6

A semiconductor device having normal and test modes, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors; and means for changing the difference in potential between said internal signal and said read reference potential, where the difference in the normal mode is different from that in the test mode.

Claim 7

A semiconductor device having normal and test modes, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors; and means for changing the difference in potential between said internal signal and said read reference potential, where the difference in the normal mode is different from that in the test mode.

Claim 8

A semiconductor device as set forth in claim 4, wherein said changing means comprises means, operatively connected to said reference potential generating means, for decreasing said read reference potential in the test mode, rather than in the normal mode.

Claim 9

A semiconductor device as set forth in claim 4, wherein said changing means comprises means, operatively connected to said word drivers, for increasing the potentials of said word lines in the test mode, rather than in the normal mode.

Claim 10

A semiconductor device having normal and test modes and operatively connectable to receive a write enable signal and a data input signal, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors, said read reference potential generating means comprising a write amplifier, operatively connectable to receive the write enable signal and the data input signal and operatively connected to the bases of said sensing transistors, for receiving the write enable signal and the data input signal, and for generating said read reference potential for the bases of said sensing transistors when the potential of the write enable signal is a potential in a read mode; and means for changing the difference in potential between said internal signal and said read reference potential, where the difference in the normal mode is different from that in the test mode.

Claim 11

A semiconductor device having normal and test modes and operatively connectable to receive a write enable signal and a data input signal, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors, said read reference potential generating means comprising a write amplifier, operatively connectable to receive the write enable signal and the data input signal and operatively connected to the bases of said sensing transistors, for receiving the write enable signal and the data input signal, and for generating said read reference potential for the bases of said sensing transistors when the potential of the write enable signal is a potential in a read mode; and means for changing the difference in potential between said internal signal and said read reference potential, where the difference in the normal mode is different from that in the test mode.

Claim 12

A semiconductor device having normal and test modes and operatively connectable to receive a first reference potential and a chip selection potential, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors; and means for changing the difference in potential between said internal signal and said read reference potential, where the difference in the normal mode is different from that in the test mode, said changing means comprising means, operatively connected to said reference potential generating means, for decreasing said read reference potential in the test mode, rather than in the normal mode, said read reference potential decreasing means comprising: a first transistor having an emitter, a collector operatively connected to said read reference potential generating means and a base for receiving the first reference potential; a second transistor having an emitter and a base for receiving the chip selection signal; and a constant current source operatively connected to the emitters of said first and second transistors; and the base potential of said second transistor being lower than the first reference potential when in the test mode.

Claim 13

A semiconductor device having normal and test modes and operatively connectable to receive a first reference potential and a chip selection potential, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors; and means for changing the difference in potential between said internal signal and said read reference potential, where the difference in the normal mode is different from that in the test mode, said changing means comprising means, operatively connected to said reference potential generating means, for decreasing said read reference potential in the test mode, rather than in the normal mode, said read reference potential decreasing means comprising: a first transistor having an emitter, a collector operatively connected to said read reference potential generating means and a base for receiving the first reference potential; a second transistor having an emitter and a base for receiving the chip selection signal; and a constant current source operatively connected to the emitters of said first and second transistors; and the base potential of said second transistor being lower than the first reference potential when in the test mode.

Claim 14

A semiconductor device having normal and test modes and operatively connectable to receive a first reference potential and a chip selection signal, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors; and means for changing the difference in potential between said internal signal and said read reference potential, where the difference in the normal mode is different from that in the test mode, said changing means comprising means, operatively connected to said reference potential generating means, for decreasing said read reference potential in the test mode, rather than in the normal mode, said read reference potential decreasing means comprising: a first transistor having an emitter, a collector operatively connected to said read reference potential generating means and a base for receiving the first reference potential; and a first load, operatively connected to the emitter of said first transistor and operatively connectable to receive the chip selection signal; and the emitter potential of said first transistor being lower than the first reference potential when in the test mode.

Claim 15

A semiconductor device having normal and test modes and operatively connectable to receive a first reference potential and a chip selection signal, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors; and means for changing the difference in potential between said internal signal and said read reference potential, where the difference in the normal mode is different from that in the test mode, said changing means comprising means, operatively connected to said reference potential generating means, for decreasing said read reference potential in the test mode, rather than in the normal mode, said read reference potential decreasing means comprising: a first transistor having an emitter, a collector operatively connected to said read reference potential generating means and a base for receiving the first reference potential; and a first load, operatively connected to the emitter of said first transistor and operatively connectable to receive the chip selection signal; and the emitter potential of said first transistor being lower than the first reference potential when in the test mode.

Claim 16

A semiconductor device having normal and test modes and operatively connectable to receive a first reference potential and having an external terminal, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors; and means for changing the difference in potential, where the difference in the normal mode is different from that in the test mode, said changing means comprising means, operatively connected to said reference potential generating means, for decreasing said read reference potential in the test mode, rather than in the normal mode, said read reference potential decreasing means comprising: a first transistor having an emitter, a collector operatively connected to said read reference potential generating means and a base for receiving the first reference potential; a second transistor having a base and an emitter; a constant current source operatively connected to the emitters of said first and second transistors; and a programmable element operatively connected to the base of said second transistor and to the external terminal, said programmable element being opened and closed in the test mode and the normal mode, respectively.

Claim 17

A semiconductor device having normal and test modes and operatively connectable to receive a first reference potential and having an external terminal, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors; and means for changing the difference in potential, where the difference in the normal mode is different from that in the test mode, said changing means comprising means, operatively connected to said reference potential generating means, for decreasing said read reference potential in the test mode, rather than in the normal mode, said read reference potential decreasing means comprising: a first transistor having an emitter, a collector operatively connected to said read reference potential generating means and a base for receiving the first reference potential; a second transistor having a base and an emitter; a constant current source operatively connected to the emitters of said first and second transistors; and a programmable element operatively connected to the base of said second transistor and to the external terminal, said programmable element being opened and closed in the test mode and the normal mode, respectively.

Claim 18

A semiconductor device as set forth in claim 10, wherein said programmable element is a diode.

Claim 19

A semiconductor device having normal and test modes and operatively connectable to receive a first reference potential and a chip selection signal, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors; and means for changing the difference in potential between said internal signal and said read reference potential, where the difference in the normal mode is different from that in the test mode, said changing means comprising means, operatively connected to said word drivers, for increasing the potentials of said word lines in the test mode, rather than in the normal mode, said word line potential increasing means comprising: a third resistor operatively connected to said word drivers; a first transistor having an emitter and a base for receiving the first reference potential; a second transistor having an emitter, a collector operatively connected to said third resistor and a base for receiving the chip selection signal; and a constant current source operatively connected to the emitters of said first and second transistors; and the base potential of said second transistor being lower than the first reference potential in the test mode.

Claim 20

A semiconductor device having normal and test modes and operatively connectable to receive a first reference potential and a chip selection signal, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors; and means for changing the difference in potential between said internal signal and said read reference potential, where the difference in the normal mode is different from that in the test mode, said changing means comprising means, operatively connected to said word drivers, for increasing the potentials of said word lines in the test mode, rather than in the normal mode, said word line potential increasing means comprising: a third resistor operatively connected to said word drivers; a first transistor having an emitter and a base for receiving the first reference potential; a second transistor having an emitter, a collector operatively connected to said third resistor and a base for receiving the chip selection signal; and a constant current source operatively connected to the emitters of said first and second transistors; and the base potential of said second transistor being lower than the first reference potential in the test mode.